Simulation Results: uart

 
20/05/2026 18:33:28 DVSim: v1.41.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.45 %
  • code
  • 94.98 %
  • assert
  • 97.12 %
  • func
  • 46.24 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 93.00 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.800s 934.166us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.900s 71.640us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.770s 87.908us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.680s 130.365us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.980s 21.889us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.950s 131.295us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.770s 87.908us 1 1 100.00
uart_csr_aliasing 0.980s 21.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 12.580s 36405.802us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.800s 934.166us 1 1 100.00
uart_tx_rx 12.580s 36405.802us 1 1 100.00
parity_error 2 2 100.00
uart_intr 10.170s 13121.785us 1 1 100.00
uart_rx_parity_err 174.190s 111649.830us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 12.580s 36405.802us 1 1 100.00
uart_intr 10.170s 13121.785us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 87.490s 111268.401us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 23.800s 16320.441us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 59.760s 147164.976us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 10.170s 13121.785us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 10.170s 13121.785us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 10.170s 13121.785us 1 1 100.00
perf 1 1 100.00
uart_perf 537.600s 13996.344us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 11.780s 10981.870us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 11.780s 10981.870us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 7.970s 45476.658us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.430s 3857.222us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.780s 834.993us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 12.940s 3555.789us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 105.180s 49042.237us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 255.940s 36831.436us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.800s 14.207us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.870s 53.891us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.370s 41.882us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.370s 41.882us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.900s 71.640us 1 1 100.00
uart_csr_rw 0.770s 87.908us 1 1 100.00
uart_csr_aliasing 0.980s 21.889us 1 1 100.00
uart_same_csr_outstanding 0.990s 39.644us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.900s 71.640us 1 1 100.00
uart_csr_rw 0.770s 87.908us 1 1 100.00
uart_csr_aliasing 0.980s 21.889us 1 1 100.00
uart_same_csr_outstanding 0.990s 39.644us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.100s 208.891us 1 1 100.00
uart_tl_intg_err 1.730s 95.361us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.730s 95.361us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 12.790s 7501.322us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_stress_all 75617334481564429976167164766637977949975513146214009070979938957289096824050 93
UVM_ERROR @ 33785744814 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 33785744814 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 33837953565 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 4
UVM_ERROR @ 33837995232 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty