Simulation Results

Simulation Results: adc_ctrl

21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
67.43 %

code
96.81 %

assert
91.73 %

func
13.74 %

line
98.99 %

branch
97.52 %

cond
87.76 %

toggle
99.76 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		50.28%
V2S		100.00%
V3		10.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	adc_ctrl_smoke	17.930s	5775.585us	10	10	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	4.230s	1051.346us	1	1	100.00
csr_rw				5	5	100.00
	adc_ctrl_csr_rw	2.280s	449.802us	5	5	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	41.720s	26735.010us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	3.380s	462.789us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	2.440s	379.507us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	adc_ctrl_csr_rw	2.280s	449.802us	5	5	100.00
	adc_ctrl_csr_aliasing	3.380s	462.789us	1	1	100.00

89/177 passed

50.28 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	10	0.00
	adc_ctrl_filters_polled	2.440s	450.770us	0	10	0.00
filters_polled_fixed				0	10	0.00
	adc_ctrl_filters_polled_fixed	2.140s	419.549us	0	10	0.00
filters_interrupt				0	10	0.00
	adc_ctrl_filters_interrupt	2.380s	518.625us	0	10	0.00
filters_interrupt_fixed				0	10	0.00
	adc_ctrl_filters_interrupt_fixed	2.110s	409.871us	0	10	0.00
filters_wakeup				0	10	0.00
	adc_ctrl_filters_wakeup	1.990s	356.726us	0	10	0.00
filters_wakeup_fixed				0	10	0.00
	adc_ctrl_filters_wakeup_fixed	2.200s	470.459us	0	10	0.00
filters_both				0	10	0.00
	adc_ctrl_filters_both	2.040s	390.192us	0	10	0.00
clock_gating				0	10	0.00
	adc_ctrl_clock_gating	2.160s	415.106us	0	10	0.00
poweron_counter				10	10	100.00
	adc_ctrl_poweron_counter	12.550s	4034.989us	10	10	100.00
lowpower_counter				10	10	100.00
	adc_ctrl_lowpower_counter	66.320s	30802.780us	10	10	100.00
fsm_reset				10	10	100.00
	adc_ctrl_fsm_reset	253.580s	133859.708us	10	10	100.00
stress_all				2	10	20.00
	adc_ctrl_stress_all	74.320s	30495.938us	2	10	20.00
alert_test				10	10	100.00
	adc_ctrl_alert_test	1.960s	333.587us	10	10	100.00
intr_test				10	10	100.00
	adc_ctrl_intr_test	2.110s	344.595us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	adc_ctrl_tl_errors	3.460s	530.216us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	adc_ctrl_tl_errors	3.460s	530.216us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	adc_ctrl_csr_hw_reset	4.230s	1051.346us	1	1	100.00
	adc_ctrl_csr_rw	2.280s	449.802us	5	5	100.00
	adc_ctrl_csr_aliasing	3.380s	462.789us	1	1	100.00
	adc_ctrl_same_csr_outstanding	15.530s	4875.308us	5	5	100.00
tl_d_partial_access				12	12	100.00
	adc_ctrl_csr_hw_reset	4.230s	1051.346us	1	1	100.00
	adc_ctrl_csr_rw	2.280s	449.802us	5	5	100.00
	adc_ctrl_csr_aliasing	3.380s	462.789us	1	1	100.00
	adc_ctrl_same_csr_outstanding	15.530s	4875.308us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	adc_ctrl_sec_cm	15.410s	4661.826us	5	5	100.00
	adc_ctrl_tl_intg_err	26.930s	8593.789us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	adc_ctrl_tl_intg_err	26.930s	8593.789us	25	25	100.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	adc_ctrl_stress_all_with_rand_reset	16.440s	5505.438us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				97 test runs
	adc_ctrl_filters_polled	23179200325170343027418821624587291754311433504223501920185269993124046457999	388	UVM_INFO @ 292057663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	67652553203100816052177813036978824119966289093926009120562607479036427900652	388	UVM_INFO @ 368199990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	85964705946068291243918992805338094054802881982205766133494018661630936610141	388	UVM_INFO @ 404214211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	58739576708703298116387646745496922013796491583465973760612284927436077494662	388	UVM_INFO @ 437031157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	42897593940877358201137619016377073375606849269935087661459663169730976743776	388	UVM_INFO @ 431572939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	55620239322066250022686380031218277257848441730949136570278258891299025024841	388	UVM_INFO @ 470459000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	89679502901935560559501258209792862916152327756482369490352446236725673062638	388	UVM_INFO @ 334702498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	87669973823581266000920359113923948335720683163835002013934263044699925730200	388	UVM_INFO @ 326944816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	54100215894406166581824385982480388250718019106381260873035994040440009667225	408	UVM_INFO @ 836799853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	79462480670391787351636274610015132056165946162348930872196889612615084444510	491	UVM_INFO @ 42827000247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	20840570063283728465447901557575977047160298557732988289841656296245877855431	388	UVM_INFO @ 450769816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	42544709291299280521175980541373664918702565457728339713175927045337022558377	388	UVM_INFO @ 391125638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	9824828983318775002947679245742023564046524865776593738666706115277005750328	388	UVM_INFO @ 459207298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	40609651968326858128507121288673545237735600591695949109905430396356038366269	388	UVM_INFO @ 293581210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	41268236056337763759938354762953964998356965935905173819789006985560749395978	388	UVM_INFO @ 355443022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	76569359463543154277461998318473781127890706925839952680423112142041998516149	388	UVM_INFO @ 489805613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	4885447390321174080215284683138771975859132459593983075296932095671990717368	388	UVM_INFO @ 360323356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	53311202405385368004756846263400599691617196167933764677548616970705773904335	388	UVM_INFO @ 449124947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	28909940189342626826468653732204086728215826066408222493784185024779848939807	394	UVM_INFO @ 678959260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	37466291568023567925475249703257377335668843833063360769588183776377332917713	389	UVM_INFO @ 768248535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	97030413797685851099615709071151419398259207882936188683694040940561203611153	388	UVM_INFO @ 332442884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	7851915021105205627554788021297764037226875553013219196390845164517557033831	388	UVM_INFO @ 421417302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	28900641528582521960664183731723553866476487972063461069884368626318745811087	388	UVM_INFO @ 422615174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	105381357895876179621246595973218004293555967183062972340890280858206585892492	388	UVM_INFO @ 400462531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	39916469051883426771547348840188073523444538119334071506979526979573057413792	388	UVM_INFO @ 435125475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	110099739482613064695448139607393646295399922045045637932509898884002517567283	388	UVM_INFO @ 415287312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	90053227881414064252799639667463231678778360313895037441100244751355584980583	388	UVM_INFO @ 491477137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	51986903055717772019755442464665836929555637822829632028229806372038179219409	388	UVM_INFO @ 363310000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	7239682895210370837177943718281099556170593431765191193036442896739812382484	408	UVM_INFO @ 2592801483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	50435969518060377837217828288895282487769566901682253177856335000870372621873	388	UVM_INFO @ 389080154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	25142986627158498604392149669027391646522007878235141114531407919530372595972	388	UVM_INFO @ 403672139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	25032893586851923536288917127826691270094851391254409445730326924042827431001	388	UVM_INFO @ 344669460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	26503270456081556408628346758516404737879805812460828138708909844142359587874	388	UVM_INFO @ 352676490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	21523697700277978961495605190865486402067778916471272953343904053031315373939	388	UVM_INFO @ 451530410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	44113514520843185011524786427953383906266560722046773405907205116334278283852	388	UVM_INFO @ 495469755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	104623196327701242909669308333616102717989526025768387106480687238507604344257	388	UVM_INFO @ 415105971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	17610813405292017273272006467861032517369769482820134889487523984871981789566	388	UVM_INFO @ 355506296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	91896366116563812557807639630275040227276142226349555318851302086439471511314	445	UVM_INFO @ 5472037876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	89849263831157898676386252370031414706851800175705653538524774408490411333338	389	UVM_INFO @ 778487025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	90312479756792512375886475161076506097632424873726194351883813864594064934613	388	UVM_INFO @ 512713863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	109925445163385798155125821416963029079455749919443022002180479746431748951247	388	UVM_INFO @ 406920132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	27024890197487462393846212778694494912908417270532603464620940500923584998724	388	UVM_INFO @ 428616845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	51093993377960363388081774485886601452377524465551492520500320974921079920985	388	UVM_INFO @ 521668745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	20532046792890995636620981764004038348667794482313452805587555863827325876929	388	UVM_INFO @ 458426269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	44557857156662994598936252978115562511316541831284640077033858435488849758692	388	UVM_INFO @ 449195315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	75015903480452854264281788556098155773979681254027947354190058578822859775660	388	UVM_INFO @ 358707493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	21892508966734155790605265871823662970743953405563166043223481638317108498141	388	UVM_INFO @ 352763097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	40719759991436056485548255352139972623000502455142006155294657347610706968084	416	UVM_INFO @ 89154557155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	110008550041233832109239905418745694572953106264061327660138476492334516639169	388	UVM_INFO @ 440533217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	86188448885820213526136611374065931572604748474390435281985197336861321789012	388	UVM_INFO @ 292242869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	32953364057423785521674004869804406300606812526361862826033446964749237782441	388	UVM_INFO @ 283152150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	19082345112857482947936949682424813619846327385525445698066672503075193372048	388	UVM_INFO @ 435005650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	114895686530583248094221833547424673763541338165923111405227079949078034437310	388	UVM_INFO @ 292582788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	54198706643665970345414764573464914546103720495536426266487315401499702332525	388	UVM_INFO @ 349480559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	38081061550353178171031504522318860505585847033831395686240571380453042053607	388	UVM_INFO @ 345863978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	98454220744465951907775444825540304204799925323757095438463456827385354965460	388	UVM_INFO @ 335274242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	48868374474435235593353222126192375890002289967775215480077523532880407908601	465	UVM_INFO @ 5505437769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	101804675910300708576829366462504961106693574461399994674032725640507753309554	389	UVM_INFO @ 542299693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	26168108006161412953772862134795194103545365074904763889949388095301801389951	388	UVM_INFO @ 485145170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	27857089427733744541569129688218062364587156312235618359179651118031292421750	388	UVM_INFO @ 375688425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	82021492253926340080979018927563611792700125242991792386534569274808867665533	388	UVM_INFO @ 408387099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	112396123803408146477837319816285210656622674109179360288085219518394324279082	388	UVM_INFO @ 409870885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	4098523313617303429304039646056803355976162812525168767172312074369798391525	388	UVM_INFO @ 525235569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	19557541584196742391580061517199319328276707387862898410391920540302335533590	388	UVM_INFO @ 398478891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	27072079052365488422700790030310486519540095381767546868470775659173245601329	388	UVM_INFO @ 403390561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	57729470052649236156639041825079029750010524860674436487134302378622489784532	388	UVM_INFO @ 293375625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	403395846440075678668969815978603341128961691455064852523273449381251898740	394	UVM_INFO @ 933356500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	114875218566085154160721709393954707850037942185588864624203098365316552702434	402	UVM_INFO @ 1242506070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	94971607643439466839330875057174239748371647672394472618192604864573094259235	388	UVM_INFO @ 446042037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	106293256503915053739021407437057993032705439873469842207210884382293237540669	388	UVM_INFO @ 428748010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	49008304678764520505349230490221773601034863724361863496983382767752067665666	388	UVM_INFO @ 458555704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	72062362922353632054294896671895028077825147330675693409324313890857629448285	388	UVM_INFO @ 372505134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	7343335901156480867918311489038162737432423346852987901467075664335912632685	388	UVM_INFO @ 356725879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	51855296506456019988936993174298356114077329860561798406552391585374146482129	388	UVM_INFO @ 346699337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	57973574604145830534636372466729905759894226087643994498652928669508583501145	388	UVM_INFO @ 367883445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	42469226339016313381625576213038544325858355211004984514384236213337973982238	388	UVM_INFO @ 360479372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	29961004126477004057384488352829828789855944222166746470745799309483034666797	394	UVM_INFO @ 818079890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	34740056085739080379796312512002864131022840899561920560642030604924678658448	389	UVM_INFO @ 950449814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	38921961555204741650735932265288647423150337861328217327380960839994324805588	388	UVM_INFO @ 312829011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	99738425732128885921532577855951478330826757767794454563634563135815174644620	388	UVM_INFO @ 386845529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	20050510351285097201370452407850763640602939922500050053425808917707639866974	388	UVM_INFO @ 518624607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	53516191921372119929631286226411821978163688674093267649416069218455851089903	388	UVM_INFO @ 523390119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	14686838381113813514644156983012266243864970807233659610832719064081805865518	388	UVM_INFO @ 363167044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	89539426679955379155267200149954349199980056613434792759766897580660154014468	388	UVM_INFO @ 345560565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	71626491859647133376947133678972200951929153205096874186447400349250693646786	388	UVM_INFO @ 331538755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	96131764284254209580588105397197845214668178972924395864604409466751066099694	388	UVM_INFO @ 390192334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	60365010173197035600715875961716367049705637089931778340329489784095884936051	401	UVM_INFO @ 765382253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	82947147355035007977680606137697125700752985442283205320512852975475330404553	389	UVM_INFO @ 661187255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	66249051709268684981264021445203995305262016623986465976915156553326355957375	388	UVM_INFO @ 276835745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	47441615067562153160729540080799816164323621391842053328306826622628317583989	388	UVM_INFO @ 419548603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	53287111416938103779258788446556636423365512184747136517085121213091206374414	388	UVM_INFO @ 483269852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	62997186340067560613363202185571796157775956541570162748960292403637660412824	388	UVM_INFO @ 458641630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	47978194384811055345506398580956882980846216342740349662168770719546990366456	388	UVM_INFO @ 341686900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	93504449312768087911497532240715621820989693917563598357815944261211279248202	388	UVM_INFO @ 510924159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	86885793424226124693384068497825532313034733191839048233907512765754325857218	388	UVM_INFO @ 322450265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	69815664239411459072848463174877153223796775791057835520529363525787872616018	388	UVM_INFO @ 326339036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	11231608402230808652653146208789609334807541860605292270655108451350994156022	394	UVM_INFO @ 925919261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---