Simulation Results: aes/masked

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 96.64 %
  • assert
  • 98.38 %
  • func
  • 98.26 %
  • block
  • 97.02 %
  • line
  • 98.06 %
  • branch
  • 92.73 %
  • toggle
  • 97.99 %
  • FSM
  • 97.78 %
Validation stages
V1
100.00%
V2
99.54%
V2S
96.12%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 113.641us 1 1 100.00
smoke 10 10 100.00
aes_smoke 5.000s 121.782us 10 10 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 11.000s 107.644us 1 1 100.00
csr_rw 5 5 100.00
aes_csr_rw 2.000s 73.082us 5 5 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 19.000s 333.989us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 25.000s 176.480us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
aes_csr_mem_rw_with_rand_reset 11.000s 207.425us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
aes_csr_rw 2.000s 73.082us 5 5 100.00
aes_csr_aliasing 25.000s 176.480us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 70 70 100.00
aes_smoke 5.000s 121.782us 10 10 100.00
aes_config_error 28.000s 88.568us 50 50 100.00
aes_stress 37.000s 1306.710us 10 10 100.00
key_length 70 70 100.00
aes_smoke 5.000s 121.782us 10 10 100.00
aes_config_error 28.000s 88.568us 50 50 100.00
aes_stress 37.000s 1306.710us 10 10 100.00
back2back 35 35 100.00
aes_stress 37.000s 1306.710us 10 10 100.00
aes_b2b 39.000s 175.945us 25 25 100.00
backpressure 10 10 100.00
aes_stress 37.000s 1306.710us 10 10 100.00
multi_message 94 95 98.95
aes_smoke 5.000s 121.782us 10 10 100.00
aes_config_error 28.000s 88.568us 50 50 100.00
aes_stress 37.000s 1306.710us 10 10 100.00
aes_alert_reset 31.000s 88.660us 24 25 96.00
failure_test 84 85 98.82
aes_man_cfg_err 7.000s 87.355us 10 10 100.00
aes_config_error 28.000s 88.568us 50 50 100.00
aes_alert_reset 31.000s 88.660us 24 25 96.00
trigger_clear_test 10 10 100.00
aes_clear 30.000s 176.084us 10 10 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 3615.005us 1 1 100.00
reset_recovery 24 25 96.00
aes_alert_reset 31.000s 88.660us 24 25 96.00
stress 10 10 100.00
aes_stress 37.000s 1306.710us 10 10 100.00
sideload 20 20 100.00
aes_stress 37.000s 1306.710us 10 10 100.00
aes_sideload 48.000s 1904.980us 10 10 100.00
deinitialization 10 10 100.00
aes_deinit 10.000s 114.130us 10 10 100.00
stress_all 10 10 100.00
aes_stress_all 61.000s 2970.754us 10 10 100.00
alert_test 10 10 100.00
aes_alert_test 28.000s 57.452us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
aes_tl_errors 5.000s 1490.755us 25 25 100.00
tl_d_illegal_access 25 25 100.00
aes_tl_errors 5.000s 1490.755us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
aes_csr_hw_reset 11.000s 107.644us 1 1 100.00
aes_csr_rw 2.000s 73.082us 5 5 100.00
aes_csr_aliasing 25.000s 176.480us 1 1 100.00
aes_same_csr_outstanding 3.000s 264.802us 5 5 100.00
tl_d_partial_access 12 12 100.00
aes_csr_hw_reset 11.000s 107.644us 1 1 100.00
aes_csr_rw 2.000s 73.082us 5 5 100.00
aes_csr_aliasing 25.000s 176.480us 1 1 100.00
aes_same_csr_outstanding 3.000s 264.802us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 10 10 100.00
aes_reseed 7.000s 150.416us 10 10 100.00
fault_inject 628 660 95.15
aes_fi 10.000s 108.688us 10 10 100.00
aes_control_fi 61.000s 0.000us 278 300 92.67
aes_cipher_fi 24.000s 75.179us 340 350 97.14
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 196.364us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 196.364us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 196.364us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 196.364us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
aes_shadow_reg_errors_with_csr_rw 16.000s 10091.879us 19 20 95.00
tl_intg_err 30 30 100.00
aes_sec_cm 8.000s 943.592us 5 5 100.00
aes_tl_intg_err 5.000s 768.733us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
aes_tl_intg_err 5.000s 768.733us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 24 25 96.00
aes_alert_reset 31.000s 88.660us 24 25 96.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 196.364us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 196.364us 20 20 100.00
sec_cm_main_config_sparse 140 145 96.55
aes_smoke 5.000s 121.782us 10 10 100.00
aes_stress 37.000s 1306.710us 10 10 100.00
aes_alert_reset 31.000s 88.660us 24 25 96.00
aes_core_fi 60.000s 10012.582us 96 100 96.00
sec_cm_gcm_config_sparse 156 160 97.50
aes_config_error 28.000s 88.568us 50 50 100.00
aes_stress 37.000s 1306.710us 10 10 100.00
aes_core_fi 60.000s 10012.582us 96 100 96.00
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 196.364us 20 20 100.00
sec_cm_aux_config_regwen 20 20 100.00
aes_readability 3.000s 71.752us 10 10 100.00
aes_stress 37.000s 1306.710us 10 10 100.00
sec_cm_key_sideload 20 20 100.00
aes_stress 37.000s 1306.710us 10 10 100.00
aes_sideload 48.000s 1904.980us 10 10 100.00
sec_cm_key_sw_unreadable 10 10 100.00
aes_readability 3.000s 71.752us 10 10 100.00
sec_cm_data_reg_sw_unreadable 10 10 100.00
aes_readability 3.000s 71.752us 10 10 100.00
sec_cm_key_sec_wipe 10 10 100.00
aes_readability 3.000s 71.752us 10 10 100.00
sec_cm_iv_config_sec_wipe 10 10 100.00
aes_readability 3.000s 71.752us 10 10 100.00
sec_cm_data_reg_sec_wipe 10 10 100.00
aes_readability 3.000s 71.752us 10 10 100.00
sec_cm_data_reg_key_sca 10 10 100.00
aes_stress 37.000s 1306.710us 10 10 100.00
sec_cm_key_masking 10 10 100.00
aes_stress 37.000s 1306.710us 10 10 100.00
sec_cm_main_fsm_sparse 10 10 100.00
aes_fi 10.000s 108.688us 10 10 100.00
sec_cm_main_fsm_redun 653 685 95.33
aes_fi 10.000s 108.688us 10 10 100.00
aes_control_fi 61.000s 0.000us 278 300 92.67
aes_cipher_fi 24.000s 75.179us 340 350 97.14
aes_ctr_fi 23.000s 60.899us 25 25 100.00
sec_cm_cipher_fsm_sparse 10 10 100.00
aes_fi 10.000s 108.688us 10 10 100.00
sec_cm_cipher_fsm_redun 628 660 95.15
aes_fi 10.000s 108.688us 10 10 100.00
aes_control_fi 61.000s 0.000us 278 300 92.67
aes_cipher_fi 24.000s 75.179us 340 350 97.14
sec_cm_cipher_ctr_redun 340 350 97.14
aes_cipher_fi 24.000s 75.179us 340 350 97.14
sec_cm_ctr_fsm_sparse 10 10 100.00
aes_fi 10.000s 108.688us 10 10 100.00
sec_cm_ctr_fsm_redun 313 335 93.43
aes_fi 10.000s 108.688us 10 10 100.00
aes_control_fi 61.000s 0.000us 278 300 92.67
aes_ctr_fi 23.000s 60.899us 25 25 100.00
sec_cm_ghash_fsm_sparse 10 10 100.00
aes_fi 10.000s 108.688us 10 10 100.00
sec_cm_ctrl_sparse 653 685 95.33
aes_fi 10.000s 108.688us 10 10 100.00
aes_control_fi 61.000s 0.000us 278 300 92.67
aes_cipher_fi 24.000s 75.179us 340 350 97.14
aes_ctr_fi 23.000s 60.899us 25 25 100.00
sec_cm_main_fsm_global_esc 24 25 96.00
aes_alert_reset 31.000s 88.660us 24 25 96.00
sec_cm_main_fsm_local_esc 653 685 95.33
aes_fi 10.000s 108.688us 10 10 100.00
aes_control_fi 61.000s 0.000us 278 300 92.67
aes_cipher_fi 24.000s 75.179us 340 350 97.14
aes_ctr_fi 23.000s 60.899us 25 25 100.00
sec_cm_cipher_fsm_local_esc 653 685 95.33
aes_fi 10.000s 108.688us 10 10 100.00
aes_control_fi 61.000s 0.000us 278 300 92.67
aes_cipher_fi 24.000s 75.179us 340 350 97.14
aes_ctr_fi 23.000s 60.899us 25 25 100.00
sec_cm_ctr_fsm_local_esc 313 335 93.43
aes_fi 10.000s 108.688us 10 10 100.00
aes_control_fi 61.000s 0.000us 278 300 92.67
aes_ctr_fi 23.000s 60.899us 25 25 100.00
sec_cm_ghash_fsm_local_esc 10 10 100.00
aes_fi 10.000s 108.688us 10 10 100.00
sec_cm_data_reg_local_esc 628 660 95.15
aes_fi 10.000s 108.688us 10 10 100.00
aes_control_fi 61.000s 0.000us 278 300 92.67
aes_cipher_fi 24.000s 75.179us 340 350 97.14
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
aes_stress_all_with_rand_reset 99.000s 9111.156us 3 10 30.00

Error Messages

   Test seed line log context
Job timed out after * minutes 12 test runs
aes_control_fi 2139827184734838575026842023846021950813074183293615218031638629541514285268 None
aes_control_fi 38283248662458218749810942565027296117229706756566747446491065435735484165325 None
aes_control_fi 100604900564600907582461234883517888118814587752828451289369547948613225773562 None
aes_control_fi 108540299338123765250996788906901956709910874129175005575120611784791118928383 None
aes_control_fi 32552107557164659579195110313207534174653847076835641052452839528532044119159 None
aes_control_fi 17197414651596186636010318038120213269774499461792909293725377121482441218382 None
aes_control_fi 90353135534551599667234790806386128442993834862797782788612864358960104383267 None
aes_control_fi 5296024986067638300588602848035120504666126457116122300168012542335895227477 None
aes_control_fi 35133256609532585557445479165423431017180731386622357958874055909631663074045 None
aes_control_fi 24185201605952894403562736344545938628699932366051748182286952126947952117602 None
aes_control_fi 85314715367588816181014776010023565641132406393320855619639448468473754526191 None
aes_control_fi 68516650697932420969325155123775033543199261620707947133090641028031451569888 None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 10 test runs
aes_cipher_fi 56546256871455554248613123281459615855265404066825614940377085769212445151069 142
UVM_INFO @ 10017142518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 55607062265464299785539540636687837059441932794512607574069223678905848539484 151
UVM_INFO @ 10049410397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 57339502284588201435325021499687085821364383429613531579330688018036257034884 141
UVM_INFO @ 10018380953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 71251445395274482753218727847237363621466043248704744984578115482477699778861 139
UVM_INFO @ 10008656664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 114593538239036197987857765924949524747469650297765311786949636052423153298947 144
UVM_INFO @ 10339914937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 68501139487407223595080037995444928882935052748436322214160821601064706178511 138
UVM_INFO @ 10044025688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 91512984942106360324741722601533323259107873324408583619973989216868381207317 147
UVM_INFO @ 10018685606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 106207025444457431002191654687202104244622918019883336824666165670713657928531 149
UVM_INFO @ 10028034344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 83378763234013479005244575844620894941553583312546897116806657919575218990565 146
UVM_INFO @ 10028620138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 96462708930224742994489624178930735418578239479607998421563324862665178947528 140
UVM_INFO @ 10010084377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 10 test runs
aes_control_fi 78707370613166170827257790963621236503374059331615454042378356518734566700759 144
UVM_INFO @ 10015967468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 90315310395273649071192114120185583799861873780299211972844007440526823532561 146
UVM_INFO @ 10007143684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 102585131715895904202729312254572139105763131922903173927005368046088090423015 145
UVM_INFO @ 10012217091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 51612822538115366788047827806334663479902891782066068614292363769768327425283 138
UVM_INFO @ 10006589104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 104933509683805522918242252938849809977653231752525541825078556365746315759146 145
UVM_INFO @ 10003866644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 57979120474227355966543734859446321717220692054991840145590199960016620727966 149
UVM_INFO @ 10031674473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 63335715714407552113755500761229520595574955582455220334295753402838785405389 142
UVM_INFO @ 10030123087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 69481490958715502005788995778444879793847025843209095441024138012393121398410 146
UVM_INFO @ 10021365422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 30483830645008811137995473594770940075893701861089365140477245715569128216522 145
UVM_INFO @ 10018282100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 14012926169849862111454028931279123175978663006153023103594485761234924463573 146
UVM_INFO @ 10009297835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 4 test runs
aes_core_fi 86779396983971962323148151025594938546222266148300350877406212834042007776787 149
UVM_INFO @ 10009499804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 13429743687989393049158399754218420470830746291447464419187099175801766529174 140
UVM_INFO @ 10036671281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 33471166811659370363583927029493539654708056950597279244696654684482335704792 141
UVM_INFO @ 10010036113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 80673226330542541250505708843515579005065375157792229204990296429984774066889 146
UVM_INFO @ 10012582240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_stress_all_with_rand_reset 67447490070774023416231834295845286477730808179457606988505438484010483309461 944
UVM_INFO @ 1927237980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 51004717522663809665740544856058972331053404841650248645531112669003753683129 1026
UVM_INFO @ 922261627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 73176214239564990670476561766654830641219245740152078987714838451061894618856 347
UVM_INFO @ 2511243046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 34784389005845583817216571572067781952068945706212629594742497139803830142905 1283
UVM_INFO @ 1019441896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
aes_stress_all_with_rand_reset 10157568275624965670252581507345864929970437603276605305856121827607180661926 218
UVM_INFO @ 445963855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 28659083852395434603712407190889802795599266308825090281552794671504236347960 1178
UVM_INFO @ 1431869123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 59029181069827443853113562313556013699023689875630591509246251063607774579222 374
UVM_INFO @ 346118676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1136): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) 1 test run
aes_alert_reset 35305127208219082601763852418413413433294740120427857626828186416113816802622 407
UVM_ERROR @ 20599986 ps: (aes_core.sv:1136) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_INFO @ 20599986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq__shadow_reg_errors.svh:336) [aes_common_vseq] ctrl_shadowed update_err alert timeout 1 test run
aes_shadow_reg_errors_with_csr_rw 44600690714443980363148030198784891625439264717914092005358998494680666358974 106
UVM_INFO @ 10091878840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---