Simulation Results: aes/unmasked

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.17 %
  • code
  • 93.11 %
  • assert
  • 97.92 %
  • func
  • 97.49 %
  • block
  • 94.18 %
  • line
  • 95.65 %
  • branch
  • 87.69 %
  • toggle
  • 97.99 %
  • FSM
  • 91.11 %
Validation stages
V1
100.00%
V2
99.54%
V2S
94.90%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 89.177us 1 1 100.00
smoke 10 10 100.00
aes_smoke 3.000s 61.753us 10 10 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 54.859us 1 1 100.00
csr_rw 5 5 100.00
aes_csr_rw 2.000s 86.225us 5 5 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 480.630us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 290.266us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 69.171us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
aes_csr_rw 2.000s 86.225us 5 5 100.00
aes_csr_aliasing 3.000s 290.266us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 70 70 100.00
aes_smoke 3.000s 61.753us 10 10 100.00
aes_config_error 4.000s 188.229us 50 50 100.00
aes_stress 4.000s 88.846us 10 10 100.00
key_length 70 70 100.00
aes_smoke 3.000s 61.753us 10 10 100.00
aes_config_error 4.000s 188.229us 50 50 100.00
aes_stress 4.000s 88.846us 10 10 100.00
back2back 35 35 100.00
aes_stress 4.000s 88.846us 10 10 100.00
aes_b2b 8.000s 135.933us 25 25 100.00
backpressure 10 10 100.00
aes_stress 4.000s 88.846us 10 10 100.00
multi_message 95 95 100.00
aes_smoke 3.000s 61.753us 10 10 100.00
aes_config_error 4.000s 188.229us 50 50 100.00
aes_stress 4.000s 88.846us 10 10 100.00
aes_alert_reset 8.000s 181.004us 25 25 100.00
failure_test 85 85 100.00
aes_man_cfg_err 2.000s 67.102us 10 10 100.00
aes_config_error 4.000s 188.229us 50 50 100.00
aes_alert_reset 8.000s 181.004us 25 25 100.00
trigger_clear_test 10 10 100.00
aes_clear 4.000s 98.161us 10 10 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 460.299us 1 1 100.00
reset_recovery 25 25 100.00
aes_alert_reset 8.000s 181.004us 25 25 100.00
stress 10 10 100.00
aes_stress 4.000s 88.846us 10 10 100.00
sideload 20 20 100.00
aes_stress 4.000s 88.846us 10 10 100.00
aes_sideload 3.000s 70.021us 10 10 100.00
deinitialization 10 10 100.00
aes_deinit 3.000s 133.594us 10 10 100.00
stress_all 9 10 90.00
aes_stress_all 446.000s 10055.112us 9 10 90.00
alert_test 10 10 100.00
aes_alert_test 8.000s 54.999us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
aes_tl_errors 4.000s 2985.132us 25 25 100.00
tl_d_illegal_access 25 25 100.00
aes_tl_errors 4.000s 2985.132us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
aes_csr_hw_reset 2.000s 54.859us 1 1 100.00
aes_csr_rw 2.000s 86.225us 5 5 100.00
aes_csr_aliasing 3.000s 290.266us 1 1 100.00
aes_same_csr_outstanding 3.000s 221.307us 5 5 100.00
tl_d_partial_access 12 12 100.00
aes_csr_hw_reset 2.000s 54.859us 1 1 100.00
aes_csr_rw 2.000s 86.225us 5 5 100.00
aes_csr_aliasing 3.000s 290.266us 1 1 100.00
aes_same_csr_outstanding 3.000s 221.307us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 10 10 100.00
aes_reseed 4.000s 80.916us 10 10 100.00
fault_inject 614 660 93.03
aes_fi 4.000s 389.205us 10 10 100.00
aes_control_fi 61.000s 0.000us 284 300 94.67
aes_cipher_fi 61.000s 0.000us 320 350 91.43
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 92.266us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 92.266us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 92.266us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 92.266us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 229.593us 20 20 100.00
tl_intg_err 30 30 100.00
aes_sec_cm 5.000s 1486.802us 5 5 100.00
aes_tl_intg_err 6.000s 923.591us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
aes_tl_intg_err 6.000s 923.591us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 25 25 100.00
aes_alert_reset 8.000s 181.004us 25 25 100.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 92.266us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 92.266us 20 20 100.00
sec_cm_main_config_sparse 141 145 97.24
aes_smoke 3.000s 61.753us 10 10 100.00
aes_stress 4.000s 88.846us 10 10 100.00
aes_alert_reset 8.000s 181.004us 25 25 100.00
aes_core_fi 159.000s 10012.404us 96 100 96.00
sec_cm_gcm_config_sparse 156 160 97.50
aes_config_error 4.000s 188.229us 50 50 100.00
aes_stress 4.000s 88.846us 10 10 100.00
aes_core_fi 159.000s 10012.404us 96 100 96.00
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 92.266us 20 20 100.00
sec_cm_aux_config_regwen 20 20 100.00
aes_readability 2.000s 69.828us 10 10 100.00
aes_stress 4.000s 88.846us 10 10 100.00
sec_cm_key_sideload 20 20 100.00
aes_stress 4.000s 88.846us 10 10 100.00
aes_sideload 3.000s 70.021us 10 10 100.00
sec_cm_key_sw_unreadable 10 10 100.00
aes_readability 2.000s 69.828us 10 10 100.00
sec_cm_data_reg_sw_unreadable 10 10 100.00
aes_readability 2.000s 69.828us 10 10 100.00
sec_cm_key_sec_wipe 10 10 100.00
aes_readability 2.000s 69.828us 10 10 100.00
sec_cm_iv_config_sec_wipe 10 10 100.00
aes_readability 2.000s 69.828us 10 10 100.00
sec_cm_data_reg_sec_wipe 10 10 100.00
aes_readability 2.000s 69.828us 10 10 100.00
sec_cm_data_reg_key_sca 10 10 100.00
aes_stress 4.000s 88.846us 10 10 100.00
sec_cm_key_masking 10 10 100.00
aes_stress 4.000s 88.846us 10 10 100.00
sec_cm_main_fsm_sparse 10 10 100.00
aes_fi 4.000s 389.205us 10 10 100.00
sec_cm_main_fsm_redun 639 685 93.28
aes_fi 4.000s 389.205us 10 10 100.00
aes_control_fi 61.000s 0.000us 284 300 94.67
aes_cipher_fi 61.000s 0.000us 320 350 91.43
aes_ctr_fi 2.000s 57.387us 25 25 100.00
sec_cm_cipher_fsm_sparse 10 10 100.00
aes_fi 4.000s 389.205us 10 10 100.00
sec_cm_cipher_fsm_redun 614 660 93.03
aes_fi 4.000s 389.205us 10 10 100.00
aes_control_fi 61.000s 0.000us 284 300 94.67
aes_cipher_fi 61.000s 0.000us 320 350 91.43
sec_cm_cipher_ctr_redun 320 350 91.43
aes_cipher_fi 61.000s 0.000us 320 350 91.43
sec_cm_ctr_fsm_sparse 10 10 100.00
aes_fi 4.000s 389.205us 10 10 100.00
sec_cm_ctr_fsm_redun 319 335 95.22
aes_fi 4.000s 389.205us 10 10 100.00
aes_control_fi 61.000s 0.000us 284 300 94.67
aes_ctr_fi 2.000s 57.387us 25 25 100.00
sec_cm_ghash_fsm_sparse 10 10 100.00
aes_fi 4.000s 389.205us 10 10 100.00
sec_cm_ctrl_sparse 639 685 93.28
aes_fi 4.000s 389.205us 10 10 100.00
aes_control_fi 61.000s 0.000us 284 300 94.67
aes_cipher_fi 61.000s 0.000us 320 350 91.43
aes_ctr_fi 2.000s 57.387us 25 25 100.00
sec_cm_main_fsm_global_esc 25 25 100.00
aes_alert_reset 8.000s 181.004us 25 25 100.00
sec_cm_main_fsm_local_esc 639 685 93.28
aes_fi 4.000s 389.205us 10 10 100.00
aes_control_fi 61.000s 0.000us 284 300 94.67
aes_cipher_fi 61.000s 0.000us 320 350 91.43
aes_ctr_fi 2.000s 57.387us 25 25 100.00
sec_cm_cipher_fsm_local_esc 639 685 93.28
aes_fi 4.000s 389.205us 10 10 100.00
aes_control_fi 61.000s 0.000us 284 300 94.67
aes_cipher_fi 61.000s 0.000us 320 350 91.43
aes_ctr_fi 2.000s 57.387us 25 25 100.00
sec_cm_ctr_fsm_local_esc 319 335 95.22
aes_fi 4.000s 389.205us 10 10 100.00
aes_control_fi 61.000s 0.000us 284 300 94.67
aes_ctr_fi 2.000s 57.387us 25 25 100.00
sec_cm_ghash_fsm_local_esc 10 10 100.00
aes_fi 4.000s 389.205us 10 10 100.00
sec_cm_data_reg_local_esc 614 660 93.03
aes_fi 4.000s 389.205us 10 10 100.00
aes_control_fi 61.000s 0.000us 284 300 94.67
aes_cipher_fi 61.000s 0.000us 320 350 91.43
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
aes_stress_all_with_rand_reset 56.000s 1317.453us 1 10 10.00

Error Messages

   Test seed line log context
Job timed out after * minutes 22 test runs
aes_control_fi 67230966449807177217506936693229602610784333611213124533932150564989852991497 None
aes_cipher_fi 97773602083152788628722859749166184180637942582729284586288890044155426642298 None
aes_cipher_fi 95183739471907274429882203635656020689579554555005321421023219641958077382280 None
aes_cipher_fi 13587439215865231393476670075155848403463668928896684819306414371169697817131 None
aes_control_fi 106031111782690081975222918050768176936776978753618900619518447456425495972598 None
aes_cipher_fi 89120977957638961355637944828223304190181671557513803986293298245467999666999 None
aes_control_fi 101321702224593277991873083324674648952959595707006733945468271096490291112811 None
aes_control_fi 8732786961015676864706237120390975906447238278518755450519415312983531790058 None
aes_cipher_fi 102376439619064782651515865669981619901023771588328404267948918020906010943555 None
aes_control_fi 36573882380235079683536218081489228453195450899156014226223167692035115511342 None
aes_control_fi 31534579517440275514545017039106759458240389942828377898623094743154075480448 None
aes_control_fi 25608638199425316316859685773227587787577302853307827787959371555838706979153 None
aes_control_fi 28349260154290656552568934834509256078790324351172535508250612503067812833403 None
aes_cipher_fi 89291146137559701541830310088066489240569673559893310727685319191391825090572 None
aes_control_fi 39855333895462402461035108294514219879804590884291344210074847093559029205785 None
aes_cipher_fi 19886613280412819254160790402996510969331048825395364413898666077006971485895 None
aes_cipher_fi 30962509708980526013838751193509501809400911533561057749202412905481768212190 None
aes_cipher_fi 90385147073774537113536492779760503990773662599616074834585062972018946170217 None
aes_cipher_fi 22450489110831094542275127604242665325101964422288219347550539882601993566455 None
aes_cipher_fi 5965668526426526153801223615288739833455778947321104792357608108627383872381 None
aes_cipher_fi 10238953002115779734809332582946486304488655936857855309511657113056661612591 None
aes_cipher_fi 37531615527831461576481953011538991549462390573781970064635247782778405752085 None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 16 test runs
aes_cipher_fi 64968669520348892112861731424285877485080099019211910257793062117688145644660 145
UVM_INFO @ 10016040160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 16587493065076436906651736248843332074245749318031791943681687117465824727546 148
UVM_INFO @ 10004183435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 95868426513009648008994364934103867236802431426503592399454458007316161344627 138
UVM_INFO @ 10002603787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 52943572444576004034370794022466119165030609704088216323971353206415238494217 146
UVM_INFO @ 10002584774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 25429260805654421173037904174327909211263700266004604035992639177382162960001 147
UVM_INFO @ 10002361271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 110460151117640224728395600969877704944718069112284408682856182196689663463148 145
UVM_INFO @ 10015304786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 18662969496246667466166138033574361051958026074521398927603098707152288830061 150
UVM_INFO @ 10007028789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 483507484422889174183074651297217217619022246810955361210353383081871771359 147
UVM_INFO @ 10030939372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 51900754173275929694341662674429557558489127595951404524586118717538520132934 142
UVM_INFO @ 10002131487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 41886134708025636766587233375169027582499708671672115516194362832000636527064 144
UVM_INFO @ 10009560547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 16502003206839342818258325970618742261705070833144998715921015866499616230110 140
UVM_INFO @ 10004150196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 21465954149783401986206437585842978169868773785347591064243577696664440031300 147
UVM_INFO @ 10010320075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 84330425151062272677759837901806319381059464521507467098231287585296793370611 147
UVM_INFO @ 10029649294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 50470293737700480959007424289019241677898282390426444740420145732780192515183 147
UVM_INFO @ 10011048109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 15656680911776543549979009992512182571064438240103511643175602305146519990470 142
UVM_INFO @ 10004938273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 2428410330294919815116069888994487954073217012546764167140866011844539387651 141
UVM_INFO @ 10017326744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 7 test runs
aes_control_fi 13732348657320483213412344444586870130553832234794134096428332346133067691656 146
UVM_INFO @ 10011375371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 52926687280459674592884399169263380752401797083081189033194074271023623382180 140
UVM_INFO @ 10003186425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 71561262120044015894208540680768488232844819650382934216630965770592718982672 144
UVM_INFO @ 10018477319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 101039957911242705859579511190732242379189095361761850980588834074765109010856 151
UVM_INFO @ 10028783062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 77991595727321992645998625787024915471464351966363532288497774414060260090338 151
UVM_INFO @ 10017450666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 62662745920554667389034511429187671633148850777931249900679946080988123925826 137
UVM_INFO @ 10041686500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 20192041762854367232223982489587456310730263661653828913320496889161024133744 141
UVM_INFO @ 10009587814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 5 test runs
aes_stress_all_with_rand_reset 49884836707371929780203913087023076843019603273125995994489360349409785708877 3908
UVM_INFO @ 4492922698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 90086378795263229892413743779902915070949112856296155450195862479424522967879 2923
UVM_INFO @ 3733334424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 8942063870971553982216651667340848587696820832073914751146030403740378648844 514
UVM_INFO @ 513071129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 51114410760051675684276450010701658241060751323681293836628994981930060720934 1241
UVM_INFO @ 1449774419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 64845271923904795849090434165979791685631223656055260872440052790439545854333 3936
UVM_INFO @ 1317452856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1142): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) 1 test run
aes_stress_all_with_rand_reset 64775793902686481519516076443471044085953002862263930023109070312961702658848 221
UVM_ERROR @ 34644105 ps: (aes_core.sv:1142) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
UVM_INFO @ 34644105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) 1 test run
aes_stress_all 40707216029663470788097372806753468674324275990966623808006290765230270251166 4807405
UVM_INFO @ 10055111740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 101728747240649763758395833909258741008208316350415739687204124211356202214590 156
UVM_INFO @ 27390574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 41961072848429230863237542663866764615001155411725313170048208971167799581894 152
UVM_INFO @ 34747747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.status reset value: * 1 test run
aes_stress_all_with_rand_reset 56386105444753022852824385346021109054326187198759703740416683323674579168654 1349
UVM_INFO @ 2420241021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) 1 test run
aes_core_fi 73804054004937679530165045729452175806572857477379950112981946017492335767146 147
UVM_INFO @ 10022396482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) 1 test run
aes_core_fi 40484789600359199760373641142817150469034125204347801481123990508854377033170 142
UVM_INFO @ 10080522539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) 1 test run
aes_core_fi 112378958184776215390025130046918749232592312471201217256020811865254089204927 140
UVM_INFO @ 10012403770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 78056279580534498948933740066206042535093784222744421885537717006422645677810 142
UVM_INFO @ 10009189164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_cipher_fi 103472417851059627973226284305043141423312250257433371327173595571938761913896 141
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---