Simulation Results

Simulation Results: clkmgr

21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
93.87 %

code
98.55 %

assert
95.76 %

func
87.31 %

line
99.07 %

branch
98.74 %

cond
95.73 %

toggle
99.19 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		78.62%
V3		100.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	2.420s	367.755us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.220s	49.448us	1	1	100.00
csr_rw				5	5	100.00
	clkmgr_csr_rw	1.910s	237.666us	5	5	100.00
csr_bit_bash				1	1	100.00
	clkmgr_csr_bit_bash	7.160s	445.550us	1	1	100.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	1.610s	86.009us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	clkmgr_csr_mem_rw_with_rand_reset	2.610s	251.716us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	clkmgr_csr_rw	1.910s	237.666us	5	5	100.00
	clkmgr_csr_aliasing	1.610s	86.009us	1	1	100.00

127/127 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	1.200s	50.506us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	1.640s	73.573us	10	10	100.00
extclk				10	10	100.00
	clkmgr_extclk	1.520s	92.646us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.280s	68.142us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	2.420s	367.755us	10	10	100.00
frequency				10	10	100.00
	clkmgr_frequency	20.960s	2480.933us	10	10	100.00
frequency_timeout				10	10	100.00
	clkmgr_frequency_timeout	10.440s	2186.754us	10	10	100.00
frequency_overflow				10	10	100.00
	clkmgr_frequency	20.960s	2480.933us	10	10	100.00
stress_all				10	10	100.00
	clkmgr_stress_all	44.270s	9429.328us	10	10	100.00
alert_test				10	10	100.00
	clkmgr_alert_test	1.440s	97.374us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	5.180s	586.832us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	5.180s	586.832us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	clkmgr_csr_hw_reset	1.220s	49.448us	1	1	100.00
	clkmgr_csr_rw	1.910s	237.666us	5	5	100.00
	clkmgr_csr_aliasing	1.610s	86.009us	1	1	100.00
	clkmgr_same_csr_outstanding	2.570s	231.252us	5	5	100.00
tl_d_partial_access				12	12	100.00
	clkmgr_csr_hw_reset	1.220s	49.448us	1	1	100.00
	clkmgr_csr_rw	1.910s	237.666us	5	5	100.00
	clkmgr_csr_aliasing	1.610s	86.009us	1	1	100.00
	clkmgr_same_csr_outstanding	2.570s	231.252us	5	5	100.00

V2S

114/145 passed

78.62 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				15	30	50.00
	clkmgr_sec_cm	1.410s	46.982us	0	5	0.00
	clkmgr_tl_intg_err	57.100s	10107.323us	15	25	60.00
shadow_reg_update_error				14	20	70.00
	clkmgr_shadow_reg_errors	840.510s	200000.000us	14	20	70.00
shadow_reg_read_clear_staged_value				14	20	70.00
	clkmgr_shadow_reg_errors	840.510s	200000.000us	14	20	70.00
shadow_reg_storage_error				14	20	70.00
	clkmgr_shadow_reg_errors	840.510s	200000.000us	14	20	70.00
shadowed_reset_glitch				14	20	70.00
	clkmgr_shadow_reg_errors	840.510s	200000.000us	14	20	70.00
shadow_reg_update_error_with_csr_rw				10	20	50.00
	clkmgr_shadow_reg_errors_with_csr_rw	1097.570s	200000.000us	10	20	50.00
sec_cm_bus_integrity				15	25	60.00
	clkmgr_tl_intg_err	57.100s	10107.323us	15	25	60.00
sec_cm_meas_clk_bkgn_chk				10	10	100.00
	clkmgr_frequency	20.960s	2480.933us	10	10	100.00
sec_cm_timeout_clk_bkgn_chk				10	10	100.00
	clkmgr_frequency_timeout	10.440s	2186.754us	10	10	100.00
sec_cm_meas_config_shadow				14	20	70.00
	clkmgr_shadow_reg_errors	840.510s	200000.000us	14	20	70.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	1.930s	170.106us	10	10	100.00
sec_cm_lc_ctrl_intersig_mubi				10	10	100.00
	clkmgr_lc_ctrl_intersig_mubi	1.550s	83.994us	10	10	100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi				10	10	100.00
	clkmgr_lc_clk_byp_req_intersig_mubi	1.670s	163.830us	10	10	100.00
sec_cm_clk_handshake_intersig_mubi				10	10	100.00
	clkmgr_clk_handshake_intersig_mubi	1.830s	202.342us	10	10	100.00
sec_cm_div_intersig_mubi				10	10	100.00
	clkmgr_div_intersig_mubi	1.450s	84.375us	10	10	100.00
sec_cm_jitter_config_mubi				5	5	100.00
	clkmgr_csr_rw	1.910s	237.666us	5	5	100.00
sec_cm_idle_ctr_redun				0	5	0.00
	clkmgr_sec_cm	1.410s	46.982us	0	5	0.00
sec_cm_meas_config_regwen				5	5	100.00
	clkmgr_csr_rw	1.910s	237.666us	5	5	100.00
sec_cm_clk_ctrl_config_regwen				5	5	100.00
	clkmgr_csr_rw	1.910s	237.666us	5	5	100.00
prim_count_check				0	5	0.00
	clkmgr_sec_cm	1.410s	46.982us	0	5	0.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				10	10	100.00
	clkmgr_regwen	8.360s	1108.614us	10	10	100.00
stress_all_with_rand_reset				10	10	100.00
	clkmgr_stress_all_with_rand_reset	187.110s	65593.363us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (cip_base_vseq.sv:1030) [clkmgr_common_vseq] timeout wait for alert handshake:fatal_fault				10 test runs
	clkmgr_tl_intg_err	1291271802881573735683832321701551030503261804893785266672259857859159159660	101	UVM_INFO @ 10016571759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	82939554091021555236503794188365963025859557944187782597231029240344072924588	123	UVM_INFO @ 10031468032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	76662253087720386381420826777847138332118047324591397364329994419030553314912	113	UVM_INFO @ 10071827021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	14429026556386775381526236740712108888622393025289231156033879279511669115548	109	UVM_INFO @ 10029883445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	25392961708761834592373319795321611795474846596112628225049938156066873655637	97	UVM_INFO @ 10027683447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	98963937630124239355144577270796738012236005758957840002892294095348120668812	89	UVM_INFO @ 10042980169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	35833828315421979621655510566035225502083510687564409149822385592901040472748	116	UVM_INFO @ 10087075447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	12335276892920679343786113463602865346654846228075536403565857193227997493303	205	UVM_INFO @ 10237162230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	58050428679200681118476336202756109501724415011460306985814721725802432462447	204	UVM_INFO @ 10107323283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	71407058621106367530236742839214051589444834486283964484926005742680445185956	121	UVM_INFO @ 10107275773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				8 test runs
	clkmgr_shadow_reg_errors	107700927228848197624164581811880685288098027867872126298378908902633060631721	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	91094269975397069254531541133993229637812671511064973828235867112298644761579	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	16837752338116596650908249655687538536733050759950235910887625471677802337580	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	86929570568854610097479361964544931685147293930738215082428556932213954406237	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	103601349181959119556542983313366952751028548883731541016475172809436019459323	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	65592144230698801922615975152971267553263322557673912960010491725565883714934	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	102554676654029369257418654948255810324218476201863952511010271978277467912398	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	62396900580619530751992971219496760361069236988776810577330199842288932084819	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire				5 test runs
	clkmgr_sec_cm	81581375032426736375974320797877023550419078234833225266062502263340915058162	100	UVM_INFO @ 38702085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	74173957906253576138507002578517963020500971992978385261874114706817786719404	97	UVM_INFO @ 46982109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	104271522975599473685456627643441704665566365804518537499325927813116969409237	85	UVM_INFO @ 15434047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	76227729447907375901223801896271498423992644625435232224327830607880154262070	80	UVM_INFO @ 8170294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	111919463995963233480042656043400241731389070224467183768635292559372778008846	98	UVM_INFO @ 25256901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_hints (addr=*)				2 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	77488475693001679437405357463788334912385335479946217737916806593390805632979	75	UVM_INFO @ 2350188057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	12953718772246627150760349397934513945553487893912052244304326389119753270662	75	UVM_INFO @ 2049156025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_enables (addr=*)				2 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	39017785199644287730821861393630133547544403290330834320185801643090876033057	76	UVM_INFO @ 3164016801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	7567027174435701728026614319260593324530916516934149149188594561570341951007	75	UVM_INFO @ 2263894440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_fault does not trigger!				2 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	85286769461274507092517609232296716116060819544800281947754066712651207783825	75	UVM_INFO @ 2847612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	47775362716145643284955577145901265241317749024029048949427761244509230921615	75	UVM_INFO @ 23111943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.measure_ctrl_regwen (addr=*)				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	76069612579417856897396605417278303429277368252385536767906328782823066591056	75	UVM_INFO @ 2109116374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: Check_csr_read_clear_staged_val task: check storage_err status				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	87022720355760552494707804200424495780716648069286757941270780833521339792825	76	UVM_INFO @ 121350007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---