Simulation Results: csrng

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.84 %
  • code
  • 96.23 %
  • assert
  • 95.85 %
  • func
  • 89.45 %
  • block
  • 98.59 %
  • line
  • 99.57 %
  • branch
  • 96.46 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.09%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 21.000s 80.964us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 31.000s 40.232us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 31.000s 25.393us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 55.000s 731.493us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 31.000s 24.020us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 31.000s 85.687us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 31.000s 25.393us 5 5 100.00
csrng_csr_aliasing 31.000s 24.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 37.000s 505.731us 200 200 100.00
alerts 500 500 100.00
csrng_alert 60.000s 4533.112us 500 500 100.00
err 500 500 100.00
csrng_err 31.000s 39.325us 500 500 100.00
cmds 0 25 0.00
csrng_cmds 33.000s 165.166us 0 25 0.00
life cycle 0 25 0.00
csrng_cmds 33.000s 165.166us 0 25 0.00
stress_all 25 25 100.00
csrng_stress_all 764.000s 41501.879us 25 25 100.00
intr_test 10 10 100.00
csrng_intr_test 28.000s 30.127us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 31.000s 15.996us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 15.000s 80.516us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 15.000s 80.516us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 31.000s 40.232us 1 1 100.00
csrng_csr_rw 31.000s 25.393us 5 5 100.00
csrng_csr_aliasing 31.000s 24.020us 1 1 100.00
csrng_same_csr_outstanding 27.000s 34.024us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 31.000s 40.232us 1 1 100.00
csrng_csr_rw 31.000s 25.393us 5 5 100.00
csrng_csr_aliasing 31.000s 24.020us 1 1 100.00
csrng_same_csr_outstanding 27.000s 34.024us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 23.000s 139.511us 5 5 100.00
csrng_tl_intg_err 12.000s 566.366us 25 25 100.00
sec_cm_config_regwen 30 30 100.00
csrng_regwen 28.000s 24.831us 25 25 100.00
csrng_csr_rw 31.000s 25.393us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 60.000s 4533.112us 500 500 100.00
sec_cm_intersig_mubi 25 25 100.00
csrng_stress_all 764.000s 41501.879us 25 25 100.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 37.000s 505.731us 200 200 100.00
csrng_err 31.000s 39.325us 500 500 100.00
csrng_sec_cm 23.000s 139.511us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 37.000s 505.731us 200 200 100.00
csrng_err 31.000s 39.325us 500 500 100.00
csrng_sec_cm 23.000s 139.511us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 37.000s 505.731us 200 200 100.00
csrng_err 31.000s 39.325us 500 500 100.00
csrng_sec_cm 23.000s 139.511us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 37.000s 505.731us 200 200 100.00
csrng_err 31.000s 39.325us 500 500 100.00
csrng_sec_cm 23.000s 139.511us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 37.000s 505.731us 200 200 100.00
csrng_err 31.000s 39.325us 500 500 100.00
csrng_sec_cm 23.000s 139.511us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 60.000s 4533.112us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 37.000s 505.731us 200 200 100.00
csrng_err 31.000s 39.325us 500 500 100.00
sec_cm_constants_lc_gated 25 25 100.00
csrng_stress_all 764.000s 41501.879us 25 25 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 60.000s 4533.112us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 12.000s 566.366us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 37.000s 505.731us 200 200 100.00
csrng_err 31.000s 39.325us 500 500 100.00
csrng_sec_cm 23.000s 139.511us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 37.000s 505.731us 200 200 100.00
csrng_err 31.000s 39.325us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 37.000s 505.731us 200 200 100.00
csrng_err 31.000s 39.325us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 37.000s 505.731us 200 200 100.00
csrng_err 31.000s 39.325us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 37.000s 505.731us 200 200 100.00
csrng_err 31.000s 39.325us 500 500 100.00
csrng_sec_cm 23.000s 139.511us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 37.000s 505.731us 200 200 100.00
csrng_err 31.000s 39.325us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 24 test runs
csrng_cmds 90051043414021389877516923416861974320508972845738186315063857906473804783246 130
UVM_INFO @ 165165614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 72441284550042026272327846139876463918698361213968007636351881962728118068996 130
UVM_INFO @ 23010378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 112027900501819249021089818442189512207385054602080011771555925121901893823658 130
UVM_INFO @ 12254924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 40424537731106974238073436571957373360659386855729250270565403132019745242099 130
UVM_INFO @ 14510532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 52047030497171917466024739972314777586772021509893256523013904862050712529669 140
UVM_INFO @ 129692529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 69156090091417525828879268926920146734731336543150251241934272010499444367765 140
UVM_INFO @ 340026443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 44540921075312146946419122001146310556157428060688422250493509938868164081479 130
UVM_INFO @ 247052262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 43604098440621274548405214451983130398285005406666542639772938556523696857873 130
UVM_INFO @ 161530983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 112051884327521020207639829258288005895146043158897866189811165117186250813878 130
UVM_INFO @ 78278594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 30020460443360685028951654449038832938137614584900744363442799315022288546229 130
UVM_INFO @ 348401638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 95758508656022607394161055691336813362816387210271084603201785952093443880573 130
UVM_INFO @ 158807173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 42751604936067080868196212776570965841493858206825182081690324249393564269168 130
UVM_INFO @ 91200162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 39047792866504166094962939120892334663146404347244627140718353609089834658621 130
UVM_INFO @ 300916422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 46292232519278435949858123549702614989921802670946252912988751420849487375804 130
UVM_INFO @ 72628089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 21337876015777868192778695715206144995478141964906657009572254951790936926354 130
UVM_INFO @ 101541613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 65037640517013756635582350683662314490757131406451916437916611130339960024496 130
UVM_INFO @ 326480868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 84431702852897461150480341685161306646225235072673814279845866314911325976464 130
UVM_INFO @ 292059630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 19188657698057382230682535708423893600983824330730773083576926526347706876177 130
UVM_INFO @ 329202735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 54443885985934414873302964501194733722520844542182061789486660002244604585594 130
UVM_INFO @ 91516265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 79397612716813166276408744108650960139756931153972198852901399583379189250878 130
UVM_INFO @ 202513375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 57033608119248564851678238202020556585631097367220593807648047403167090751196 130
UVM_INFO @ 60755546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 33823030605162546117229835077044705929890431229953795190596135941430192920207 130
UVM_INFO @ 161765954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 59023626218826036463949344229771114122508568535237827399547788366483923852007 130
UVM_INFO @ 180142581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 34424904030514619953206948110701488054558630679073685193924790659452580039445 130
UVM_INFO @ 26114118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 9 test runs
csrng_stress_all_with_rand_reset 62272165707084292162708819033226205212586248083794040311839043590603222750895 None
csrng_stress_all_with_rand_reset 101591100980571756211246572116247687799390558387924869411795772654093138781940 None
csrng_stress_all_with_rand_reset 12095322282560259006373382369529969540217798613978011659136287577271853544936 None
csrng_stress_all_with_rand_reset 49051779679624266282945816151828526201622157270985606207975449048903780623672 None
csrng_stress_all_with_rand_reset 88636484292557369840294012110350750402368020486633373174462653903054288897738 None
csrng_stress_all_with_rand_reset 72258529262077792763081512110979514573932083675371399972485535836919450465410 None
csrng_stress_all_with_rand_reset 3361558963968115755698556733057509174713768528879570908506899810645725467172 None
csrng_stress_all_with_rand_reset 61142859438862632815760225468056400485910573193296858993490073510701429750976 None
csrng_stress_all_with_rand_reset 71858578569098052005308438831794860340330851789231897472881034501520623319102 None
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 1 test run
csrng_cmds 12087469587529347601809038750164376409476903316166019136073280280290981816780 139
UVM_INFO @ 46063537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 106821106958712896130909764124890561415334400404220406069411803517282167022413 105
UVM_INFO @ 14182680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---