Simulation Results: edn/edn0

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.37 %
  • code
  • 95.63 %
  • assert
  • 97.61 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.12 %
  • FSM
  • 91.40 %
Validation stages
V1
100.00%
V2
98.85%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.460s 18.555us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.290s 66.970us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.100s 13.432us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.050s 250.617us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.540s 133.316us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.550s 125.641us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.100s 13.432us 5 5 100.00
edn_csr_aliasing 1.540s 133.316us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 3.030s 96.322us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 3.030s 96.322us 100 100 100.00
genbits 100 100 100.00
edn_genbits 3.030s 96.322us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.400s 21.439us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.800s 409.190us 200 200 100.00
errs 100 100 100.00
edn_err 1.480s 46.689us 100 100 100.00
disable 93 100 93.00
edn_disable 1.340s 13.745us 50 50 100.00
edn_disable_auto_req_mode 7.490s 500.000us 43 50 86.00
stress_all 30 30 100.00
edn_stress_all 8.290s 374.718us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.240s 53.489us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.720s 58.705us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.300s 118.268us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.300s 118.268us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.290s 66.970us 1 1 100.00
edn_csr_rw 1.100s 13.432us 5 5 100.00
edn_csr_aliasing 1.540s 133.316us 1 1 100.00
edn_same_csr_outstanding 1.530s 27.847us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.290s 66.970us 1 1 100.00
edn_csr_rw 1.100s 13.432us 5 5 100.00
edn_csr_aliasing 1.540s 133.316us 1 1 100.00
edn_same_csr_outstanding 1.530s 27.847us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 8.420s 3031.318us 5 5 100.00
edn_tl_intg_err 2.560s 145.955us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.310s 43.148us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.800s 409.190us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.420s 3031.318us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.420s 3031.318us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 8.420s 3031.318us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 8.420s 3031.318us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.800s 409.190us 200 200 100.00
edn_sec_cm 8.420s 3031.318us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.800s 409.190us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 2.560s 145.955us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 30 66.67
edn_stress_all_with_rand_reset 85.200s 31871.642us 20 30 66.67

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 7 test runs
edn_stress_all_with_rand_reset 87262475813532053111299652562224876332066699521555376291292214220986010003213 150
UVM_INFO @ 1596242039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 71450649191203410858813470317481772823743888547508929754324536409135623812031 145
UVM_INFO @ 568476220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 68072049868430982583552997599118519338532068286425395743556407951820552717529 131
UVM_INFO @ 867222770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 61500341623416196551962445640978692003805503067360745820890552309950004550935 205
UVM_INFO @ 2196170044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 98175563159737588054931324260733614027621107890856131205770737359796358303545 180
UVM_INFO @ 2095906751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 102355452514178588059235693579393214042730497631378461537042537013012248796322 136
UVM_INFO @ 637165309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 15788353780882948372644203436430808054943834362297031453118873217713471062302 172
UVM_INFO @ 2009270036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
edn_disable_auto_req_mode 14573039006999719797767410240645146180829095347026193297211736854288763059628 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 62137228155600378696781828359565975393877051249563618298363213186226326183617 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 62871743523781174416645714811913429038301114510009216356623704288345541473403 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 89310020494252676165769828910455182399022582536143444615867024368829281417610 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 73740692153987354280591433725520771145254118821746922139795264175797481876133 88
UVM_INFO @ 17610075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 20986792325287473073309279933578896847296838837425405834090032964917176898108 88
UVM_INFO @ 35700453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 20600080014218536615621804848631999871098255208776022451529515763160032292285 88
UVM_INFO @ 26063669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [edn_common_vseq] wait timeout occurred! 2 test runs
edn_stress_all_with_rand_reset 27765183083084504805309017631683454595721781458528774008574583356987031396749 208
UVM_INFO @ 11993227568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 54308272673849373763424637441187314339954910707380408182297815260452455893152 192
UVM_INFO @ 12654079008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_stress_all_with_rand_reset 22528039641356085273261396729252866324700499120027569839636457164120526818641 147
/nightly/current_run/scratch/reseed_opt/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 38538718 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup