Simulation Results

Simulation Results: edn/edn1

21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
95.24 %

code
96.15 %

assert
97.14 %

func
92.44 %

line
98.48 %

branch
94.59 %

cond
95.00 %

toggle
96.08 %

FSM
96.59 %

Validation stages

V1		100.00%
V2		98.85%
V2S		100.00%
V3		80.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	edn_smoke	1.140s	19.484us	10	10	100.00
csr_hw_reset				1	1	100.00
	edn_csr_hw_reset	0.790s	16.527us	1	1	100.00
csr_rw				5	5	100.00
	edn_csr_rw	0.940s	24.712us	5	5	100.00
csr_bit_bash				1	1	100.00
	edn_csr_bit_bash	2.140s	98.050us	1	1	100.00
csr_aliasing				1	1	100.00
	edn_csr_aliasing	1.020s	33.550us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	edn_csr_mem_rw_with_rand_reset	1.400s	54.544us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	edn_csr_rw	0.940s	24.712us	5	5	100.00
	edn_csr_aliasing	1.020s	33.550us	1	1	100.00

600/607 passed

98.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
firmware				100	100	100.00
	edn_genbits	3.000s	417.540us	100	100	100.00
csrng_commands				100	100	100.00
	edn_genbits	3.000s	417.540us	100	100	100.00
genbits				100	100	100.00
	edn_genbits	3.000s	417.540us	100	100	100.00
interrupts				20	20	100.00
	edn_intr	1.180s	24.393us	20	20	100.00
alerts				200	200	100.00
	edn_alert	1.570s	30.556us	200	200	100.00
errs				100	100	100.00
	edn_err	1.460s	58.277us	100	100	100.00
disable				93	100	93.00
	edn_disable	1.190s	43.151us	50	50	100.00
	edn_disable_auto_req_mode	14.940s	500.000us	43	50	86.00
stress_all				30	30	100.00
	edn_stress_all	7.060s	484.283us	30	30	100.00
intr_test				10	10	100.00
	edn_intr_test	1.190s	56.317us	10	10	100.00
alert_test				10	10	100.00
	edn_alert_test	1.260s	18.628us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	edn_tl_errors	3.600s	124.232us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	edn_tl_errors	3.600s	124.232us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	edn_csr_hw_reset	0.790s	16.527us	1	1	100.00
	edn_csr_rw	0.940s	24.712us	5	5	100.00
	edn_csr_aliasing	1.020s	33.550us	1	1	100.00
	edn_same_csr_outstanding	1.340s	39.877us	5	5	100.00
tl_d_partial_access				12	12	100.00
	edn_csr_hw_reset	0.790s	16.527us	1	1	100.00
	edn_csr_rw	0.940s	24.712us	5	5	100.00
	edn_csr_aliasing	1.020s	33.550us	1	1	100.00
	edn_same_csr_outstanding	1.340s	39.877us	5	5	100.00

V2S

235/235 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	edn_sec_cm	3.840s	342.128us	5	5	100.00
	edn_tl_intg_err	2.550s	164.753us	25	25	100.00
sec_cm_config_regwen				5	5	100.00
	edn_regwen	1.140s	31.631us	5	5	100.00
sec_cm_config_mubi				200	200	100.00
	edn_alert	1.570s	30.556us	200	200	100.00
sec_cm_main_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	3.840s	342.128us	5	5	100.00
sec_cm_ack_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	3.840s	342.128us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	edn_sec_cm	3.840s	342.128us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	edn_sec_cm	3.840s	342.128us	5	5	100.00
sec_cm_main_sm_ctr_local_esc				205	205	100.00
	edn_alert	1.570s	30.556us	200	200	100.00
	edn_sec_cm	3.840s	342.128us	5	5	100.00
sec_cm_cs_rdata_bus_consistency				200	200	100.00
	edn_alert	1.570s	30.556us	200	200	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	edn_tl_intg_err	2.550s	164.753us	25	25	100.00

24/30 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				24	30	80.00
	edn_stress_all_with_rand_reset	90.990s	20017.422us	24	30	80.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				6 test runs
	edn_stress_all_with_rand_reset	64473661669379695669186868095243405205707678672725827334664046235591596959785	128	UVM_INFO @ 1021215326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	12585835636946344638891976783587168415510372648996677285089638329044793701430	127	UVM_INFO @ 766816964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	52000484121825060396695991635265789330869970273877285298696107566688580862620	184	UVM_INFO @ 2117802407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	48051476692272442287232238773611442109346038134382374958220991885891568898716	229	UVM_INFO @ 1504000228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	36608735368554047270152444269641407801484061477462289823292082868824467249397	140	UVM_INFO @ 1099855186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	80413022462085216523608501044843203008887065621841585335436635742028050698613	163	UVM_INFO @ 831106780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				4 test runs
	edn_disable_auto_req_mode	20905195722910454123893410761971415733179308700551107061361277842205547544900	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	50768334681043539967133910118795169757277861477247249539079270470816772338647	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	23768964074723700802607077188381437402338059994579312931233159631659402835732	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	110985057006979995600442114079729485400147200606913213892114210701187155632199	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.				3 test runs
	edn_disable_auto_req_mode	64158760086608466356844185318766267064561669619060831131858007319567219589490	88	UVM_INFO @ 84619545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	40890151538299683796773986797255964078231564739364408271808085072520582537890	88	UVM_INFO @ 18361594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	6027808941380579894603234952125438740694398257602485441662365578363463132481	88	UVM_INFO @ 49876517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---