Simulation Results: flash_ctrl

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.03 %
  • code
  • 95.88 %
  • assert
  • 96.76 %
  • func
  • 98.45 %
  • line
  • 96.10 %
  • branch
  • 97.45 %
  • cond
  • 94.80 %
  • toggle
  • 98.52 %
  • FSM
  • 92.52 %
Validation stages
V1
100.00%
V2
99.14%
V2S
98.53%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
flash_ctrl_smoke 139.750s 28.448us 50 50 100.00
smoke_hw 5 5 100.00
flash_ctrl_smoke_hw 24.810s 17.909us 5 5 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 19.020s 226.778us 1 1 100.00
csr_rw 5 5 100.00
flash_ctrl_csr_rw 11.840s 58.862us 5 5 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 99.630s 12125.046us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 29.880s 727.004us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 18.020s 50.263us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
flash_ctrl_csr_rw 11.840s 58.862us 5 5 100.00
flash_ctrl_csr_aliasing 29.880s 727.004us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 11.680s 16.543us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 8.030s 36.025us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 5 5 100.00
flash_ctrl_sw_op 26.920s 26.458us 5 5 100.00
host_read_direct 5 5 100.00
flash_ctrl_host_dir_rd 60.020s 245.650us 5 5 100.00
rma_hw_if 43 43 100.00
flash_ctrl_hw_rma 1630.230s 127746.771us 3 3 100.00
flash_ctrl_hw_rma_reset 772.210s 160204.105us 20 20 100.00
flash_ctrl_lcmgr_intg 13.480s 70.650us 20 20 100.00
host_controller_arb 5 5 100.00
flash_ctrl_host_ctrl_arb 1917.320s 267658.278us 5 5 100.00
erase_suspend 5 5 100.00
flash_ctrl_erase_suspend 357.780s 8013.979us 5 5 100.00
program_reset 29 30 96.67
flash_ctrl_prog_reset 3604.012s 0.000us 29 30 96.67
full_memory_access 5 5 100.00
flash_ctrl_full_mem_access 3597.040s 49894.888us 5 5 100.00
rd_buff_eviction 5 5 100.00
flash_ctrl_rd_buff_evict 175.260s 5418.093us 5 5 100.00
rd_buff_eviction_w_ecc 105 105 100.00
flash_ctrl_rw_evict 31.170s 28.068us 40 40 100.00
flash_ctrl_rw_evict_all_en 32.530s 28.616us 40 40 100.00
flash_ctrl_re_evict 35.550s 74.343us 25 25 100.00
host_arb 20 20 100.00
flash_ctrl_phy_arb 261.330s 1399.702us 20 20 100.00
host_interleave 20 20 100.00
flash_ctrl_phy_arb 261.330s 1399.702us 20 20 100.00
memory_protection 20 20 100.00
flash_ctrl_mp_regions 614.330s 39341.880us 20 20 100.00
fetch_code 10 10 100.00
flash_ctrl_fetch_code 22.530s 724.496us 10 10 100.00
all_partitions 20 20 100.00
flash_ctrl_rand_ops 704.900s 2419.030us 20 20 100.00
error_mp 10 10 100.00
flash_ctrl_error_mp 619.710s 4830.512us 10 10 100.00
error_prog_win 10 10 100.00
flash_ctrl_error_prog_win 497.580s 7999.609us 10 10 100.00
error_prog_type 5 5 100.00
flash_ctrl_error_prog_type 1304.930s 1379.081us 5 5 100.00
error_read_seed 20 20 100.00
flash_ctrl_hw_read_seed_err 13.880s 76.782us 20 20 100.00
read_write_overflow 5 5 100.00
flash_ctrl_oversize_error 172.780s 8738.029us 5 5 100.00
flash_ctrl_disable 50 50 100.00
flash_ctrl_disable 22.260s 62.190us 50 50 100.00
flash_ctrl_connect 80 80 100.00
flash_ctrl_connect 17.280s 15.979us 80 80 100.00
stress_all 5 5 100.00
flash_ctrl_stress_all 902.460s 1468.874us 5 5 100.00
secret_partition 129 130 99.23
flash_ctrl_hw_sec_otp 201.560s 12917.974us 50 50 100.00
flash_ctrl_otp_reset 103.270s 65.645us 79 80 98.75
isolation_partition 3 3 100.00
flash_ctrl_hw_rma 1630.230s 127746.771us 3 3 100.00
interrupts 99 100 99.00
flash_ctrl_intr_rd 183.410s 26860.748us 40 40 100.00
flash_ctrl_intr_wr 77.240s 13625.681us 10 10 100.00
flash_ctrl_intr_rd_slow_flash 370.430s 79889.221us 40 40 100.00
flash_ctrl_intr_wr_slow_flash 3604.011s 0.000us 9 10 90.00
invalid_op 20 20 100.00
flash_ctrl_invalid_op 75.500s 1748.623us 20 20 100.00
mid_op_rst 5 5 100.00
flash_ctrl_mid_op_rst 62.160s 1340.284us 5 5 100.00
double_bit_err 34 35 97.14
flash_ctrl_read_word_sweep_derr 20.820s 89.840us 5 5 100.00
flash_ctrl_ro_derr 128.960s 8112.606us 10 10 100.00
flash_ctrl_rw_derr 3604.011s 0.000us 9 10 90.00
flash_ctrl_derr_detect 186.090s 4856.161us 5 5 100.00
flash_ctrl_integrity 551.240s 88299.679us 5 5 100.00
single_bit_err 25 25 100.00
flash_ctrl_read_word_sweep_serr 21.200s 36.442us 5 5 100.00
flash_ctrl_ro_serr 116.450s 1480.584us 10 10 100.00
flash_ctrl_rw_serr 195.940s 1696.987us 10 10 100.00
singlebit_err_counter 5 5 100.00
flash_ctrl_serr_counter 88.500s 8878.944us 5 5 100.00
singlebit_err_address 4 5 80.00
flash_ctrl_serr_address 3604.013s 0.000us 4 5 80.00
scramble 59 62 95.16
flash_ctrl_wo 3099.940s 200000.000us 18 20 90.00
flash_ctrl_write_word_sweep 9.770s 91.278us 1 1 100.00
flash_ctrl_read_word_sweep 7.740s 49.379us 1 1 100.00
flash_ctrl_ro 114.110s 10628.058us 20 20 100.00
flash_ctrl_rw 509.870s 28271.389us 19 20 95.00
filesystem_support 5 5 100.00
flash_ctrl_fs_sup 33.930s 1215.333us 5 5 100.00
rma_write_process_error 23 23 100.00
flash_ctrl_rma_err 746.620s 87562.951us 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 254.510s 10018.522us 20 20 100.00
alert_test 10 10 100.00
flash_ctrl_alert_test 12.810s 24.526us 10 10 100.00
intr_test 10 10 100.00
flash_ctrl_intr_test 13.240s 18.093us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
flash_ctrl_tl_errors 20.040s 147.967us 25 25 100.00
tl_d_illegal_access 25 25 100.00
flash_ctrl_tl_errors 20.040s 147.967us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
flash_ctrl_csr_hw_reset 19.020s 226.778us 1 1 100.00
flash_ctrl_csr_rw 11.840s 58.862us 5 5 100.00
flash_ctrl_csr_aliasing 29.880s 727.004us 1 1 100.00
flash_ctrl_same_csr_outstanding 16.500s 674.352us 5 5 100.00
tl_d_partial_access 12 12 100.00
flash_ctrl_csr_hw_reset 19.020s 226.778us 1 1 100.00
flash_ctrl_csr_rw 11.840s 58.862us 5 5 100.00
flash_ctrl_csr_aliasing 29.880s 727.004us 1 1 100.00
flash_ctrl_same_csr_outstanding 16.500s 674.352us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
flash_ctrl_shadow_reg_errors 83.300s 76.944us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
flash_ctrl_shadow_reg_errors 83.300s 76.944us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
flash_ctrl_shadow_reg_errors 83.300s 76.944us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
flash_ctrl_shadow_reg_errors 83.300s 76.944us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 81.310s 1455.491us 20 20 100.00
tl_intg_err 28 30 93.33
flash_ctrl_sec_cm 2353.950s 3393.560us 3 5 60.00
flash_ctrl_tl_intg_err 568.770s 859.263us 25 25 100.00
sec_cm_reg_bus_integrity 25 25 100.00
flash_ctrl_tl_intg_err 568.770s 859.263us 25 25 100.00
sec_cm_host_bus_integrity 25 25 100.00
flash_ctrl_tl_intg_err 568.770s 859.263us 25 25 100.00
sec_cm_mem_bus_integrity 6 6 100.00
flash_ctrl_rd_intg 28.580s 171.551us 3 3 100.00
flash_ctrl_wr_intg 14.620s 296.345us 3 3 100.00
sec_cm_scramble_key_sideload 50 50 100.00
flash_ctrl_smoke 139.750s 28.448us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 259 260 99.62
flash_ctrl_otp_reset 103.270s 65.645us 79 80 98.75
flash_ctrl_disable 22.260s 62.190us 50 50 100.00
flash_ctrl_sec_info_access 80.400s 4066.543us 50 50 100.00
flash_ctrl_connect 17.280s 15.979us 80 80 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
flash_ctrl_config_regwen 12.870s 73.542us 5 5 100.00
sec_cm_data_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 11.840s 58.862us 5 5 100.00
sec_cm_data_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 83.300s 76.944us 20 20 100.00
sec_cm_info_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 11.840s 58.862us 5 5 100.00
sec_cm_info_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 83.300s 76.944us 20 20 100.00
sec_cm_bank_config_regwen 5 5 100.00
flash_ctrl_csr_rw 11.840s 58.862us 5 5 100.00
sec_cm_bank_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 83.300s 76.944us 20 20 100.00
sec_cm_mem_ctrl_global_esc 50 50 100.00
flash_ctrl_disable 22.260s 62.190us 50 50 100.00
sec_cm_mem_ctrl_local_esc 6 6 100.00
flash_ctrl_rd_intg 28.580s 171.551us 3 3 100.00
flash_ctrl_access_after_disable 12.530s 63.339us 3 3 100.00
sec_cm_mem_addr_infection 3 3 100.00
flash_ctrl_host_addr_infection 27.350s 191.139us 3 3 100.00
sec_cm_mem_disable_config_mubi 50 50 100.00
flash_ctrl_disable 22.260s 62.190us 50 50 100.00
sec_cm_exec_config_redun 10 10 100.00
flash_ctrl_fetch_code 22.530s 724.496us 10 10 100.00
sec_cm_mem_scramble 19 20 95.00
flash_ctrl_rw 509.870s 28271.389us 19 20 95.00
sec_cm_mem_integrity 24 25 96.00
flash_ctrl_rw_serr 195.940s 1696.987us 10 10 100.00
flash_ctrl_rw_derr 3604.011s 0.000us 9 10 90.00
flash_ctrl_integrity 551.240s 88299.679us 5 5 100.00
sec_cm_rma_entry_mem_sec_wipe 3 3 100.00
flash_ctrl_hw_rma 1630.230s 127746.771us 3 3 100.00
sec_cm_ctrl_fsm_sparse 3 5 60.00
flash_ctrl_sec_cm 2353.950s 3393.560us 3 5 60.00
sec_cm_phy_fsm_sparse 3 5 60.00
flash_ctrl_sec_cm 2353.950s 3393.560us 3 5 60.00
sec_cm_phy_prog_fsm_sparse 3 5 60.00
flash_ctrl_sec_cm 2353.950s 3393.560us 3 5 60.00
sec_cm_ctr_redun 3 5 60.00
flash_ctrl_sec_cm 2353.950s 3393.560us 3 5 60.00
sec_cm_phy_arbiter_ctrl_redun 5 5 100.00
flash_ctrl_phy_arb_redun 25.770s 873.834us 5 5 100.00
sec_cm_phy_host_grant_ctrl_consistency 3 5 60.00
flash_ctrl_phy_host_grant_err 12.910s 23.493us 3 5 60.00
sec_cm_phy_ack_ctrl_consistency 5 5 100.00
flash_ctrl_phy_ack_consistency 12.560s 53.500us 5 5 100.00
sec_cm_fifo_ctr_redun 3 5 60.00
flash_ctrl_sec_cm 2353.950s 3393.560us 3 5 60.00
sec_cm_mem_tl_lc_gate_fsm_sparse 3 5 60.00
flash_ctrl_sec_cm 2353.950s 3393.560us 3 5 60.00
sec_cm_prog_tl_lc_gate_fsm_sparse 3 5 60.00
flash_ctrl_sec_cm 2353.950s 3393.560us 3 5 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 36.190s 29.539us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 3 100.00
flash_ctrl_basic_rw 396.330s 1393.836us 3 3 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 4 test runs
flash_ctrl_prog_reset 107388911674744212443330240171420835074289614414751844270102274713792974274653 None
flash_ctrl_serr_address 84871051535321816845333997553917047450504399079375844504549846374030646533393 None
flash_ctrl_rw_derr 63946659905711799121962173007544861301938023974194818787698549488432254728123 None
flash_ctrl_intr_wr_slow_flash 19637806474296596593857409069271914721037676370520521201362304799328963635502 None
UVM_ERROR (alert_receiver_driver.sv:262) driver [driver] m_transaction_tasks nonempty after reset: '{*:*} 2 test runs
flash_ctrl_sec_cm 48806031095142876565154416323145963527529799850610734054078399846224870593111 1961
UVM_INFO @ 356406.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_sec_cm 68807526176312473714887219215506913556358275376661190164854000886298420863364 6273
UVM_INFO @ 1074573.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' 2 test runs
flash_ctrl_phy_host_grant_err 55314200974983221633498725101220940475923907697606011377791800604429423066862 125
UVM_ERROR @ 19320.6 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 19320.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_phy_host_grant_err 38988303067616639850778772854545883574718219806997660376095340613675378003107 125
UVM_ERROR @ 9867.9 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 9867.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue 2 test runs
flash_ctrl_wo 5623223756953895773741560671892010611997189330175524253706531739939007774033 108
UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_wo 49011616276118984696646401360194993134521891933717721206504754599689083482570 108
UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly 1 test run
flash_ctrl_rw 11468285089132772727002280302907871910685041712607294734567710657578140640413 108
UVM_INFO @ 4464838.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'dst_req_o' 1 test run
flash_ctrl_otp_reset 69683206905217313083488490115173862500243360160550184225527683514954073620530 124
UVM_ERROR @ 20068.3 ns: (prim_sync_reqack.sv:355) [ASSERT FAILED] SyncReqAckAckNeedsReq
UVM_INFO @ 20068.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---