Simulation Results: gpio

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.37 %
  • code
  • 98.27 %
  • assert
  • 96.84 %
  • func
  • 100.00 %
  • line
  • 99.76 %
  • branch
  • 99.80 %
  • cond
  • 99.57 %
  • toggle
  • 93.94 %
Validation stages
V1
100.00%
V2
94.90%
V2S
100.00%
V3
35.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 40 40 100.00
gpio_smoke 1.630s 47.919us 10 10 100.00
gpio_smoke_no_pullup_pulldown 1.480s 510.040us 10 10 100.00
gpio_smoke_en_cdc_prim 1.740s 614.436us 10 10 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.530s 46.423us 10 10 100.00
csr_hw_reset 1 1 100.00
gpio_csr_hw_reset 0.970s 48.545us 1 1 100.00
csr_rw 5 5 100.00
gpio_csr_rw 0.980s 20.000us 5 5 100.00
csr_bit_bash 1 1 100.00
gpio_csr_bit_bash 1.810s 34.932us 1 1 100.00
csr_aliasing 1 1 100.00
gpio_csr_aliasing 1.320s 32.504us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
gpio_csr_mem_rw_with_rand_reset 1.310s 41.128us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
gpio_csr_rw 0.980s 20.000us 5 5 100.00
gpio_csr_aliasing 1.320s 32.504us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 20 20 100.00
gpio_random_dout_din 1.670s 253.016us 10 10 100.00
gpio_random_dout_din_no_pullup_pulldown 1.310s 244.672us 10 10 100.00
out_in_regs_read_write 10 10 100.00
gpio_dout_din_regs_random_rw 1.250s 38.406us 10 10 100.00
gpio_interrupt_programming 10 10 100.00
gpio_intr_rand_pgm 1.310s 31.776us 10 10 100.00
random_interrupt_trigger 10 10 100.00
gpio_rand_intr_trigger 3.160s 135.169us 10 10 100.00
interrupt_and_noise_filter 10 10 100.00
gpio_intr_with_filter_rand_intr_event 3.890s 86.028us 10 10 100.00
noise_filter_stress 10 10 100.00
gpio_filter_stress 28.630s 990.825us 10 10 100.00
regs_long_reads_and_writes 10 10 100.00
gpio_random_long_reg_writes_reg_reads 5.350s 327.730us 10 10 100.00
full_random 10 10 100.00
gpio_full_random 1.260s 137.072us 10 10 100.00
stress_all 2 10 20.00
gpio_stress_all 67.310s 29840.673us 2 10 20.00
alert_test 10 10 100.00
gpio_alert_test 0.950s 36.759us 10 10 100.00
intr_test 10 10 100.00
gpio_intr_test 1.000s 29.368us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
gpio_tl_errors 3.850s 197.716us 25 25 100.00
tl_d_illegal_access 25 25 100.00
gpio_tl_errors 3.850s 197.716us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
gpio_csr_rw 0.980s 20.000us 5 5 100.00
gpio_same_csr_outstanding 1.150s 61.989us 5 5 100.00
gpio_csr_aliasing 1.320s 32.504us 1 1 100.00
gpio_csr_hw_reset 0.970s 48.545us 1 1 100.00
tl_d_partial_access 12 12 100.00
gpio_csr_rw 0.980s 20.000us 5 5 100.00
gpio_same_csr_outstanding 1.150s 61.989us 5 5 100.00
gpio_csr_aliasing 1.320s 32.504us 1 1 100.00
gpio_csr_hw_reset 0.970s 48.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
gpio_tl_intg_err 1.830s 108.473us 25 25 100.00
gpio_sec_cm 1.400s 202.593us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
gpio_tl_intg_err 1.830s 108.473us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 7 10 70.00
gpio_rand_straps 0.950s 49.461us 7 10 70.00
stress_all_with_rand_reset 0 10 0.00
gpio_stress_all_with_rand_reset 6.910s 783.976us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 11 test runs
gpio_stress_all 50741752896727949816385638467926188880525936611371837873505896271053127815630 1035
UVM_INFO @ 3059313301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 35928244278347089790773737134092705765740755999570504802295781975311103071585 80
UVM_INFO @ 739738537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 13621094275874920756063350797452768210004486674346017128136959657041910622105 456
UVM_INFO @ 2508426093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 24610684554181951323739464351554727797687501285412387892363271256814325070442 759
UVM_INFO @ 8551608929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 18988359105409306574165920555506031008285786718962241415698575953258711013993 75
UVM_INFO @ 12085970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 71981319330855594081831582444463417547779930911718134353342301294924690957711 81
UVM_INFO @ 4130877705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 100543878837608676754828751396253521234264898563646759874243993847379671051843 75
UVM_INFO @ 4832147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 86727371129783540978489195807330919494879593497425053916727096656597842159444 989
UVM_INFO @ 12608220996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 30835259267502614506701807756922178937250009330303082540347158862569907821210 1700
UVM_INFO @ 9418428940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 131637509388781520374605873532174911753451779380794594569566338021430643910 75
UVM_INFO @ 19447227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 96596782375084704441420179359511604284632468447499051980901989025113485432152 1589
UVM_INFO @ 4028278719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 6 test runs
gpio_stress_all_with_rand_reset 63390180095734226638886951005614872529930838824293027267633178502900773975224 80
UVM_INFO @ 1296695442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 43471495357596345672332931103619292885787595198690065821494674098255505358297 78
UVM_INFO @ 5973173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 68366491929955774560168655996923688550384053696816545847587873988925706710003 78
UVM_INFO @ 144787044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 66781606132182303174147351109361847349804769267057326100651571278091931607982 84
UVM_INFO @ 4447846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 66494835803621378646343379907000290183858086136396884541856127359240053031665 81
UVM_INFO @ 783976042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 100315698490601610168592463884848140437908152022398106831837749315126358536406 79
UVM_INFO @ 95665347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [gpio_common_vseq] Check failed (vseq_done) 4 test runs
gpio_stress_all_with_rand_reset 13215124782912885360380732600752638706594631936560001210048034178062330640736 80
UVM_INFO @ 3385194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 76610077890941511453460141561694408588768806764965746258225963837901268918699 96
UVM_INFO @ 466857761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 98448207412114647091687935317411764713284846309169450265810049978954900083162 83
UVM_INFO @ 5105873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 11596011117845286676946871165112406356587295372640631059265557730714512119410 86
UVM_INFO @ 6044149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---