Simulation Results: hmac

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.84 %
  • code
  • 98.73 %
  • assert
  • 97.80 %
  • func
  • 100.00 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.85 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
98.57%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 12.810s 5099.187us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.020s 15.548us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.200s 30.708us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.210s 4182.473us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 7.040s 1466.353us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 143.660s 16981.691us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.200s 30.708us 5 5 100.00
hmac_csr_aliasing 7.040s 1466.353us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 93.190s 6066.204us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 83.770s 4381.394us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 256.660s 33768.001us 30 30 100.00
hmac_test_sha384_vectors 538.260s 14287.627us 75 75 100.00
hmac_test_sha512_vectors 542.690s 115503.409us 75 75 100.00
hmac_test_hmac256_vectors 15.830s 1605.193us 50 50 100.00
hmac_test_hmac384_vectors 17.090s 421.182us 60 60 100.00
hmac_test_hmac512_vectors 18.530s 2561.387us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 43.350s 9098.678us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 863.310s 4761.599us 10 10 100.00
error 10 10 100.00
hmac_error 104.310s 36118.502us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 151.490s 12057.136us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 12.810s 5099.187us 10 10 100.00
hmac_long_msg 93.190s 6066.204us 10 10 100.00
hmac_back_pressure 83.770s 4381.394us 25 25 100.00
hmac_datapath_stress 863.310s 4761.599us 10 10 100.00
hmac_burst_wr 43.350s 9098.678us 50 50 100.00
hmac_stress_all 1962.800s 45301.215us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 12.810s 5099.187us 10 10 100.00
hmac_long_msg 93.190s 6066.204us 10 10 100.00
hmac_back_pressure 83.770s 4381.394us 25 25 100.00
hmac_datapath_stress 863.310s 4761.599us 10 10 100.00
hmac_wipe_secret 151.490s 12057.136us 10 10 100.00
hmac_test_sha256_vectors 256.660s 33768.001us 30 30 100.00
hmac_test_sha384_vectors 538.260s 14287.627us 75 75 100.00
hmac_test_sha512_vectors 542.690s 115503.409us 75 75 100.00
hmac_test_hmac256_vectors 15.830s 1605.193us 50 50 100.00
hmac_test_hmac384_vectors 17.090s 421.182us 60 60 100.00
hmac_test_hmac512_vectors 18.530s 2561.387us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 12.810s 5099.187us 10 10 100.00
hmac_long_msg 93.190s 6066.204us 10 10 100.00
hmac_back_pressure 83.770s 4381.394us 25 25 100.00
hmac_datapath_stress 863.310s 4761.599us 10 10 100.00
hmac_burst_wr 43.350s 9098.678us 50 50 100.00
hmac_error 104.310s 36118.502us 10 10 100.00
hmac_wipe_secret 151.490s 12057.136us 10 10 100.00
hmac_test_sha256_vectors 256.660s 33768.001us 30 30 100.00
hmac_test_sha384_vectors 538.260s 14287.627us 75 75 100.00
hmac_test_sha512_vectors 542.690s 115503.409us 75 75 100.00
hmac_test_hmac256_vectors 15.830s 1605.193us 50 50 100.00
hmac_test_hmac384_vectors 17.090s 421.182us 60 60 100.00
hmac_test_hmac512_vectors 18.530s 2561.387us 75 75 100.00
hmac_stress_all 1962.800s 45301.215us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1962.800s 45301.215us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.960s 15.439us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 1.010s 19.771us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 4.060s 218.926us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 4.060s 218.926us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.020s 15.548us 1 1 100.00
hmac_csr_rw 1.200s 30.708us 5 5 100.00
hmac_csr_aliasing 7.040s 1466.353us 1 1 100.00
hmac_same_csr_outstanding 2.790s 49.713us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.020s 15.548us 1 1 100.00
hmac_csr_rw 1.200s 30.708us 5 5 100.00
hmac_csr_aliasing 7.040s 1466.353us 1 1 100.00
hmac_same_csr_outstanding 2.790s 49.713us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.340s 99.998us 5 5 100.00
hmac_tl_intg_err 5.160s 869.227us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.160s 869.227us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 12.810s 5099.187us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.200s 144.525us 25 25 100.00
stress_all_with_rand_reset 34 35 97.14
hmac_stress_all_with_rand_reset 452.560s 6336.671us 34 35 97.14
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.940s 28.746us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [hmac_common_vseq] wait timeout occurred! 1 test run
hmac_stress_all_with_rand_reset 42579423874435498573783004447732928108105451414533627354350049927430661567488 2440
UVM_INFO @ 15412201240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---