Simulation Results: keymgr

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.95 %
  • code
  • 98.97 %
  • assert
  • 97.72 %
  • func
  • 91.16 %
  • line
  • 99.20 %
  • branch
  • 99.00 %
  • cond
  • 97.80 %
  • toggle
  • 98.85 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.06%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 30 30 100.00
keymgr_smoke 31.790s 4768.520us 30 30 100.00
random 30 30 100.00
keymgr_random 41.240s 2181.059us 30 30 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.340s 95.081us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.290s 123.639us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 5.490s 1187.617us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 13.420s 1819.856us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 2.390s 513.962us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.290s 123.639us 5 5 100.00
keymgr_csr_aliasing 13.420s 1819.856us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 58.370s 5746.620us 50 50 100.00
sideload 80 80 100.00
keymgr_sideload 46.200s 8696.628us 20 20 100.00
keymgr_sideload_kmac 26.500s 11755.965us 20 20 100.00
keymgr_sideload_aes 44.950s 1734.889us 20 20 100.00
keymgr_sideload_otbn 18.530s 1008.812us 20 20 100.00
direct_to_disabled_state 29 30 96.67
keymgr_direct_to_disabled 15.200s 2428.795us 29 30 96.67
lc_disable 50 50 100.00
keymgr_lc_disable 20.320s 2067.619us 50 50 100.00
kmac_error_response 20 20 100.00
keymgr_kmac_rsp_err 5.130s 112.954us 20 20 100.00
invalid_sw_input 20 20 100.00
keymgr_sw_invalid_input 39.130s 1818.259us 20 20 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 40.290s 30695.014us 50 50 100.00
sync_async_fault_cross 19 20 95.00
keymgr_sync_async_fault_cross 7.520s 317.520us 19 20 95.00
stress_all 48 50 96.00
keymgr_stress_all 587.010s 99644.352us 48 50 96.00
intr_test 10 10 100.00
keymgr_intr_test 1.090s 12.612us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.290s 22.908us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 3.620s 121.462us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 3.620s 121.462us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.340s 95.081us 1 1 100.00
keymgr_csr_rw 1.290s 123.639us 5 5 100.00
keymgr_csr_aliasing 13.420s 1819.856us 1 1 100.00
keymgr_same_csr_outstanding 3.650s 205.684us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.340s 95.081us 1 1 100.00
keymgr_csr_rw 1.290s 123.639us 5 5 100.00
keymgr_csr_aliasing 13.420s 1819.856us 1 1 100.00
keymgr_same_csr_outstanding 3.650s 205.684us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 9.050s 473.848us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 9.050s 473.848us 5 5 100.00
keymgr_tl_intg_err 7.880s 1606.041us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 5.100s 824.129us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 5.100s 824.129us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 5.100s 824.129us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 5.100s 824.129us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 14.260s 514.042us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 9.050s 473.848us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 9.050s 473.848us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 7.880s 1606.041us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 5.100s 824.129us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 58.370s 5746.620us 50 50 100.00
sec_cm_reseed_config_regwen 35 35 100.00
keymgr_random 41.240s 2181.059us 30 30 100.00
keymgr_csr_rw 1.290s 123.639us 5 5 100.00
sec_cm_sw_binding_config_regwen 35 35 100.00
keymgr_random 41.240s 2181.059us 30 30 100.00
keymgr_csr_rw 1.290s 123.639us 5 5 100.00
sec_cm_max_key_ver_config_regwen 35 35 100.00
keymgr_random 41.240s 2181.059us 30 30 100.00
keymgr_csr_rw 1.290s 123.639us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
keymgr_lc_disable 20.320s 2067.619us 50 50 100.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 40.290s 30695.014us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 40.290s 30695.014us 50 50 100.00
sec_cm_hw_key_sw_noaccess 30 30 100.00
keymgr_random 41.240s 2181.059us 30 30 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 8.490s 1581.770us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 9.050s 473.848us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 9.050s 473.848us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 9.050s 473.848us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 38.990s 2362.964us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 50 50 100.00
keymgr_lc_disable 20.320s 2067.619us 50 50 100.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 9.050s 473.848us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 9.050s 473.848us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 9.050s 473.848us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 38.990s 2362.964us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 38.990s 2362.964us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 9.050s 473.848us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 38.990s 2362.964us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 9.050s 473.848us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 38.990s 2362.964us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 14 20 70.00
keymgr_stress_all_with_rand_reset 25.040s 4180.515us 14 20 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
keymgr_stress_all_with_rand_reset 73253617808808941475143732438331575037776743238447469664564956373968348877802 247
UVM_INFO @ 135238766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 19796861278699088414209284089180075912901393155460581881081553094865347151531 233
UVM_INFO @ 198416779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 43862040366193657298377628608253963243251639543153119988483023307060537988695 382
UVM_INFO @ 792208275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 99334719097420386139636631753218072330003981415405795002270773453524268247670 363
UVM_INFO @ 269774184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 113121957782407096124589345748959183139196863502240187593897385394139603606970 798
UVM_INFO @ 2836389624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 47977942643255455613703104291347923645714705141885955202019516717587841056974 282
UVM_INFO @ 462058394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 2 test runs
keymgr_stress_all 16059382903929476718521347548057911487402525731388078504225063795139175676020 2688
UVM_INFO @ 1423366060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_direct_to_disabled 15372396506709133150478278583477314898500229845751627760101330740329072284726 94
UVM_INFO @ 11876297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received! 1 test run
keymgr_sync_async_fault_cross 45189782733283651686938569122684924908685621443328008691737343957073145279162 132
UVM_INFO @ 86347157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StCreatorRootKey for Attestation Kmac 1 test run
keymgr_stress_all 926042070510785005677323116646407434070799348047660506541629024366900918429 468
UVM_INFO @ 169601016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---