Simulation Results: kmac/masked

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.79 %
  • code
  • 94.39 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 80.99 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 84.580s 7231.456us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.990s 21.342us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.540s 30.184us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 17.220s 1459.755us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 6.530s 143.903us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 3.040s 88.322us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.540s 30.184us 5 5 100.00
kmac_csr_aliasing 6.530s 143.903us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.920s 11.650us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.190s 37.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 3942.740s 87534.963us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 950.920s 22555.706us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2677.470s 90814.227us 5 5 100.00
kmac_test_vectors_sha3_256 2604.610s 97255.488us 5 5 100.00
kmac_test_vectors_sha3_384 1221.890s 16338.824us 5 5 100.00
kmac_test_vectors_sha3_512 1127.690s 126518.746us 5 5 100.00
kmac_test_vectors_shake_128 2311.250s 21717.754us 5 5 100.00
kmac_test_vectors_shake_256 2727.120s 182325.337us 5 5 100.00
kmac_test_vectors_kmac 3.020s 152.852us 5 5 100.00
kmac_test_vectors_kmac_xof 4.080s 1694.480us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 419.540s 226868.362us 20 20 100.00
app 25 25 100.00
kmac_app 373.800s 69923.057us 25 25 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 290.290s 24295.888us 10 10 100.00
entropy_refresh 20 20 100.00
kmac_entropy_refresh 328.900s 15495.328us 20 20 100.00
error 20 20 100.00
kmac_error 489.630s 20772.718us 20 20 100.00
key_error 20 20 100.00
kmac_key_error 13.870s 10953.949us 20 20 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.150s 254.492us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 36.080s 1026.120us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 47.890s 1646.426us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 54.700s 21061.089us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 24.710s 4190.176us 50 50 100.00
stress_all 20 20 100.00
kmac_stress_all 2510.600s 78091.412us 20 20 100.00
intr_test 10 10 100.00
kmac_intr_test 1.180s 40.785us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.200s 50.684us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
kmac_tl_errors 4.290s 657.765us 25 25 100.00
tl_d_illegal_access 25 25 100.00
kmac_tl_errors 4.290s 657.765us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 0.990s 21.342us 1 1 100.00
kmac_csr_rw 1.540s 30.184us 5 5 100.00
kmac_csr_aliasing 6.530s 143.903us 1 1 100.00
kmac_same_csr_outstanding 2.830s 125.639us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 0.990s 21.342us 1 1 100.00
kmac_csr_rw 1.540s 30.184us 5 5 100.00
kmac_csr_aliasing 6.530s 143.903us 1 1 100.00
kmac_same_csr_outstanding 2.830s 125.639us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.870s 455.535us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.870s 455.535us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.870s 455.535us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.870s 455.535us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.380s 829.975us 20 20 100.00
tl_intg_err 30 30 100.00
kmac_sec_cm 114.230s 14070.812us 5 5 100.00
kmac_tl_intg_err 6.210s 343.136us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
kmac_tl_intg_err 6.210s 343.136us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 24.710s 4190.176us 50 50 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 84.580s 7231.456us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 419.540s 226868.362us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.870s 455.535us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 114.230s 14070.812us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 114.230s 14070.812us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 114.230s 14070.812us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 84.580s 7231.456us 20 20 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 24.710s 4190.176us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 114.230s 14070.812us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 345.430s 15484.598us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 84.580s 7231.456us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 332.720s 5269.581us 8 10 80.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [kmac_common_vseq] wait timeout occurred! 1 test run
kmac_stress_all_with_rand_reset 47076023872738399669237258543979322868218459812958737325027288255995657024901 213
UVM_INFO @ 16080923446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 1 test run
kmac_stress_all_with_rand_reset 54942306263766472992164277632504673809689624761488346487327620242267017690040 355
UVM_INFO @ 18013162633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---