Simulation Results: kmac/unmasked

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.50 %
  • code
  • 92.34 %
  • assert
  • 97.90 %
  • func
  • 96.25 %
  • line
  • 97.56 %
  • branch
  • 95.85 %
  • cond
  • 94.75 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
97.87%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 60.170s 2590.687us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.300s 25.739us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.550s 62.978us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 8.020s 759.322us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 10.150s 470.045us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 3.030s 71.597us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.550s 62.978us 5 5 100.00
kmac_csr_aliasing 10.150s 470.045us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 1.070s 21.455us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.990s 133.026us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 3546.660s 429347.636us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 909.930s 72569.111us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2327.730s 362872.371us 5 5 100.00
kmac_test_vectors_sha3_256 2375.600s 90587.503us 5 5 100.00
kmac_test_vectors_sha3_384 952.340s 27541.352us 5 5 100.00
kmac_test_vectors_sha3_512 1041.520s 226548.978us 5 5 100.00
kmac_test_vectors_shake_128 215.600s 39736.493us 5 5 100.00
kmac_test_vectors_shake_256 339.220s 15466.682us 5 5 100.00
kmac_test_vectors_kmac 2.880s 371.607us 5 5 100.00
kmac_test_vectors_kmac_xof 2.790s 331.382us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 372.040s 18759.205us 20 20 100.00
app 25 25 100.00
kmac_app 241.700s 35567.791us 25 25 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 308.560s 36740.386us 10 10 100.00
entropy_refresh 20 20 100.00
kmac_entropy_refresh 284.090s 135278.979us 20 20 100.00
error 20 20 100.00
kmac_error 316.180s 15776.653us 20 20 100.00
key_error 20 20 100.00
kmac_key_error 10.540s 1669.746us 20 20 100.00
sideload_invalid 41 50 82.00
kmac_sideload_invalid 105.550s 10094.728us 41 50 82.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 50.750s 14498.351us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 37.870s 7608.675us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 85.990s 8235.935us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 44.940s 4005.148us 50 50 100.00
stress_all 20 20 100.00
kmac_stress_all 2471.600s 155448.149us 20 20 100.00
intr_test 10 10 100.00
kmac_intr_test 1.160s 26.684us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.190s 175.639us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
kmac_tl_errors 4.500s 2304.671us 25 25 100.00
tl_d_illegal_access 25 25 100.00
kmac_tl_errors 4.500s 2304.671us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 1.300s 25.739us 1 1 100.00
kmac_csr_rw 1.550s 62.978us 5 5 100.00
kmac_csr_aliasing 10.150s 470.045us 1 1 100.00
kmac_same_csr_outstanding 3.240s 425.912us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 1.300s 25.739us 1 1 100.00
kmac_csr_rw 1.550s 62.978us 5 5 100.00
kmac_csr_aliasing 10.150s 470.045us 1 1 100.00
kmac_same_csr_outstanding 3.240s 425.912us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.780s 331.370us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.780s 331.370us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.780s 331.370us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.780s 331.370us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.910s 909.921us 20 20 100.00
tl_intg_err 30 30 100.00
kmac_sec_cm 56.000s 5937.154us 5 5 100.00
kmac_tl_intg_err 6.120s 328.637us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
kmac_tl_intg_err 6.120s 328.637us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 44.940s 4005.148us 50 50 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 60.170s 2590.687us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 372.040s 18759.205us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.780s 331.370us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 56.000s 5937.154us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 56.000s 5937.154us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 56.000s 5937.154us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 60.170s 2590.687us 20 20 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 44.940s 4005.148us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 56.000s 5937.154us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 213.140s 16118.347us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 60.170s 2590.687us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 291.150s 37336.335us 8 10 80.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) 3 test runs
kmac_sideload_invalid 36273044530866994216491872057593921593677920668750167771097596384033311433925 79
UVM_INFO @ 10093945149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 30319680477153852800597725415101017218066770985198805283768042111475208917111 79
UVM_INFO @ 10050740082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 27754990812405145385901933535830554964498699955713164628083300463037381309129 79
UVM_INFO @ 10089663333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) 2 test runs
kmac_sideload_invalid 50593366397508408123884214421778074949336793754925083965432762817104155610185 84
UVM_INFO @ 10113173503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 52608521825806705415789642186641331457311581402378150220737687651502771917576 84
UVM_INFO @ 10838389783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [kmac_common_vseq] wait timeout occurred! 1 test run
kmac_stress_all_with_rand_reset 13067175624175724088454035155915605748226530913115456345517728333527742057062 104
UVM_INFO @ 10550185773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 44888016402256710190980040051463842591901565847368419406256308160232036045077 256
UVM_INFO @ 12921954056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
kmac_sideload_invalid 14696931030728718000671951848537564502928914208899553172048912509802353905586 85
UVM_INFO @ 10149360725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) 1 test run
kmac_sideload_invalid 59109482397195318194536106902426586671937369489764931897271686131935300470823 91
UVM_INFO @ 10094728016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 1 test run
kmac_sideload_invalid 66440160963873021813939298206980622649859665221406493125700313196314227749959 78
UVM_INFO @ 10008046362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) 1 test run
kmac_sideload_invalid 86161581297732927450357249113360993540535689635917215932126801573113821117342 98
UVM_INFO @ 10490886245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---