Simulation Results: lc_ctrl/volatile_unlock_disabled

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.20 %
  • code
  • 86.20 %
  • assert
  • 94.13 %
  • func
  • 96.26 %
  • line
  • 97.28 %
  • branch
  • 94.14 %
  • cond
  • 81.84 %
  • toggle
  • 89.54 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 3.230s 343.598us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.100s 49.227us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.450s 45.914us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.520s 72.266us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.720s 109.801us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.460s 31.546us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.450s 45.914us 5 5 100.00
lc_ctrl_csr_aliasing 1.720s 109.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 10.300s 100.363us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 15.030s 1397.240us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.270s 36.716us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.740s 303.157us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 13.120s 1494.156us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 20.910s 1395.718us 20 20 100.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 13.120s 1494.156us 20 20 100.00
lc_ctrl_prog_failure 4.740s 303.157us 20 20 100.00
lc_ctrl_errors 20.910s 1395.718us 20 20 100.00
lc_ctrl_security_escalation 10.630s 935.443us 20 20 100.00
lc_ctrl_jtag_state_failure 84.820s 6213.955us 20 20 100.00
lc_ctrl_jtag_prog_failure 12.640s 1875.927us 20 20 100.00
lc_ctrl_jtag_errors 52.160s 6337.346us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 12.240s 502.647us 20 20 100.00
lc_ctrl_jtag_state_post_trans 17.450s 511.704us 20 20 100.00
lc_ctrl_jtag_prog_failure 12.640s 1875.927us 20 20 100.00
lc_ctrl_jtag_errors 52.160s 6337.346us 19 20 95.00
lc_ctrl_jtag_access 14.150s 11620.702us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 26.870s 4981.251us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.560s 350.621us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.320s 431.448us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 23.540s 3686.848us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 10.710s 600.014us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.800s 45.272us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.870s 662.365us 10 10 100.00
lc_ctrl_jtag_alert_test 2.460s 99.397us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 26.330s 11055.507us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.370s 11.675us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 437.040s 40117.814us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.560s 77.656us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.770s 301.399us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.770s 301.399us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.100s 49.227us 1 1 100.00
lc_ctrl_csr_rw 1.450s 45.914us 5 5 100.00
lc_ctrl_csr_aliasing 1.720s 109.801us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.280s 231.429us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.100s 49.227us 1 1 100.00
lc_ctrl_csr_rw 1.450s 45.914us 5 5 100.00
lc_ctrl_csr_aliasing 1.720s 109.801us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.280s 231.429us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 14.390s 405.017us 5 5 100.00
lc_ctrl_tl_intg_err 3.830s 217.702us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.830s 217.702us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 15.030s 1397.240us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 13.120s 1494.156us 20 20 100.00
lc_ctrl_sec_cm 14.390s 405.017us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 13.120s 1494.156us 20 20 100.00
lc_ctrl_sec_cm 14.390s 405.017us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.120s 1494.156us 20 20 100.00
lc_ctrl_sec_cm 14.390s 405.017us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.120s 1494.156us 20 20 100.00
lc_ctrl_sec_cm 14.390s 405.017us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 13.120s 1494.156us 20 20 100.00
lc_ctrl_sec_cm 14.390s 405.017us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.120s 1494.156us 20 20 100.00
lc_ctrl_sec_cm 14.390s 405.017us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.120s 1494.156us 20 20 100.00
lc_ctrl_sec_cm 14.390s 405.017us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 13.120s 1494.156us 20 20 100.00
lc_ctrl_sec_cm 14.390s 405.017us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 10.630s 935.443us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 10.300s 100.363us 20 20 100.00
lc_ctrl_jtag_state_post_trans 17.450s 511.704us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 18.230s 1275.704us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 18.230s 1275.704us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 14.410s 1054.282us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.260s 434.249us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.260s 434.249us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 68.990s 6294.061us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 49493599026069396822048589728671459285012849853142174847493037946948630818589 2398
UVM_INFO @ 1412012931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 107902856581430099724717658983333740719726830308455088142575795927908099962350 2988
UVM_INFO @ 1136361551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19207156384395132839029777268935475211622367951523497922368195925708769549489 5417
UVM_INFO @ 6074611391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 69349369731438087976915746963761960717617342673082901536464376021657483959891 5607
UVM_INFO @ 6294060715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_stress_all 106554216423006523907609325755759696387364799425373569532758907230356202381073 426
UVM_INFO @ 944038813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 94918400063257603699323540706722945058918138392031293265658986918376179573604 1990
UVM_INFO @ 1509444378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 95694886617828420955018224432817588200410606003634151265967951448638532439503 5105
UVM_INFO @ 1542537501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---