Simulation Results: lc_ctrl/volatile_unlock_enabled

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.19 %
  • code
  • 86.35 %
  • assert
  • 94.13 %
  • func
  • 96.09 %
  • line
  • 97.26 %
  • branch
  • 93.95 %
  • cond
  • 81.83 %
  • toggle
  • 89.54 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.06%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.870s 249.347us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.190s 92.870us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.200s 13.690us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.420s 91.861us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.730s 32.223us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.650s 34.214us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.200s 13.690us 5 5 100.00
lc_ctrl_csr_aliasing 1.730s 32.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 7.890s 433.712us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 22.450s 970.577us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.250s 14.549us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.580s 658.775us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 12.200s 315.090us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 17.840s 702.839us 19 20 95.00
security_escalation 137 140 97.86
lc_ctrl_state_failure 12.200s 315.090us 20 20 100.00
lc_ctrl_prog_failure 3.580s 658.775us 20 20 100.00
lc_ctrl_errors 17.840s 702.839us 19 20 95.00
lc_ctrl_security_escalation 10.370s 765.345us 20 20 100.00
lc_ctrl_jtag_state_failure 75.090s 4829.511us 20 20 100.00
lc_ctrl_jtag_prog_failure 19.290s 887.762us 20 20 100.00
lc_ctrl_jtag_errors 59.460s 11100.367us 18 20 90.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 13.800s 2803.557us 20 20 100.00
lc_ctrl_jtag_state_post_trans 27.350s 1110.744us 20 20 100.00
lc_ctrl_jtag_prog_failure 19.290s 887.762us 20 20 100.00
lc_ctrl_jtag_errors 59.460s 11100.367us 18 20 90.00
lc_ctrl_jtag_access 20.760s 1177.500us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 26.250s 1356.308us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.100s 564.781us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.300s 181.081us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 27.090s 3027.816us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 9.200s 358.393us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.810s 187.687us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.460s 1145.633us 10 10 100.00
lc_ctrl_jtag_alert_test 1.970s 107.511us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 30.200s 1709.326us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.320s 149.981us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 411.940s 55152.332us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.330s 66.585us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.360s 649.876us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.360s 649.876us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.190s 92.870us 1 1 100.00
lc_ctrl_csr_rw 1.200s 13.690us 5 5 100.00
lc_ctrl_csr_aliasing 1.730s 32.223us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.610s 86.412us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.190s 92.870us 1 1 100.00
lc_ctrl_csr_rw 1.200s 13.690us 5 5 100.00
lc_ctrl_csr_aliasing 1.730s 32.223us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.610s 86.412us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 6.370s 245.152us 5 5 100.00
lc_ctrl_tl_intg_err 3.250s 87.767us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.250s 87.767us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 22.450s 970.577us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 12.200s 315.090us 20 20 100.00
lc_ctrl_sec_cm 6.370s 245.152us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 12.200s 315.090us 20 20 100.00
lc_ctrl_sec_cm 6.370s 245.152us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.200s 315.090us 20 20 100.00
lc_ctrl_sec_cm 6.370s 245.152us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.200s 315.090us 20 20 100.00
lc_ctrl_sec_cm 6.370s 245.152us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 12.200s 315.090us 20 20 100.00
lc_ctrl_sec_cm 6.370s 245.152us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.200s 315.090us 20 20 100.00
lc_ctrl_sec_cm 6.370s 245.152us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.200s 315.090us 20 20 100.00
lc_ctrl_sec_cm 6.370s 245.152us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 12.200s 315.090us 20 20 100.00
lc_ctrl_sec_cm 6.370s 245.152us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 10.370s 765.345us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 7.890s 433.712us 20 20 100.00
lc_ctrl_jtag_state_post_trans 27.350s 1110.744us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.160s 683.480us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.160s 683.480us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 9.990s 571.874us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.400s 6918.127us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.400s 6918.127us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 84.690s 5525.562us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
lc_ctrl_stress_all_with_rand_reset 5417350783597121671046761777345199324347712630999166522478917635231463893219 985
UVM_INFO @ 4639627297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 31674248826826923956543101071586806919426214719060096270936922394337292165280 199
UVM_INFO @ 109256985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 102278994009934336862438257805176226774958279414671188432498729712698296809568 1537
UVM_INFO @ 1200972575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 99669399478409461664680308268774716548351700287425735615988999664067836944490 211
UVM_INFO @ 470158200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 67440584142059542004218819681675512856958435638729877202509619186311475400918 7765
UVM_INFO @ 5525562172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 99777995035983914164984035410821469910876649319741994722590945968452136603021 9404
UVM_INFO @ 2569643884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 4 test runs
lc_ctrl_errors 50186114676493360452920063443677230311518238000935962216546718810956462176381 2254
UVM_INFO @ 754414689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 67849405704160163724172438098938861489185199104483899931105292720786983523218 1721
UVM_INFO @ 3575100661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 2036164553979121651181205434192500249108069089120218675629919113109385667606 238
UVM_INFO @ 1892638837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 88427503296883891460958554080302706298197124250585402778531635621820878949442 2779
UVM_INFO @ 6009896919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---