Simulation Results: otbn

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.69 %
  • code
  • 96.63 %
  • assert
  • 90.43 %
  • func
  • 100.00 %
  • block
  • 99.50 %
  • line
  • 99.62 %
  • branch
  • 93.65 %
  • toggle
  • 93.25 %
  • FSM
  • 100.00 %
Validation stages
V1
99.14%
V2
98.16%
V2S
96.66%
V3
50.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 68.000s 163.304us 1 1 100.00
single_binary 99 100 99.00
otbn_single 50.000s 97.996us 99 100 99.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 39.000s 27.407us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 38.000s 41.926us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 41.000s 58.700us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 39.000s 20.658us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 44.000s 34.774us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 38.000s 41.926us 5 5 100.00
otbn_csr_aliasing 39.000s 20.658us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 102.000s 4724.142us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 57.000s 513.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 65.000s 367.834us 10 10 100.00
multi_error 0 1 0.00
otbn_multi_err 45.000s 42.393us 0 1 0.00
back_to_back 10 10 100.00
otbn_multi 172.000s 469.819us 10 10 100.00
stress_all 9 10 90.00
otbn_stress_all 3422.000s 10010.750us 9 10 90.00
lc_escalation 59 60 98.33
otbn_escalate 39.000s 27.533us 59 60 98.33
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 34.000s 61.326us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 46.000s 43.742us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 40.000s 20.021us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 39.000s 18.418us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 35.000s 256.692us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 35.000s 256.692us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 39.000s 27.407us 1 1 100.00
otbn_csr_rw 38.000s 41.926us 5 5 100.00
otbn_csr_aliasing 39.000s 20.658us 1 1 100.00
otbn_same_csr_outstanding 38.000s 38.032us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 39.000s 27.407us 1 1 100.00
otbn_csr_rw 38.000s 41.926us 5 5 100.00
otbn_csr_aliasing 39.000s 20.658us 1 1 100.00
otbn_same_csr_outstanding 38.000s 38.032us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 42.000s 21.056us 10 10 100.00
otbn_dmem_err 41.000s 19.188us 15 15 100.00
internal_integrity 14 17 82.35
otbn_alu_bignum_mod_err 41.000s 83.028us 4 5 80.00
otbn_controller_ispr_rdata_err 40.000s 77.985us 4 5 80.00
otbn_mac_bignum_acc_err 41.000s 73.449us 4 5 80.00
otbn_urnd_err 30.000s 89.291us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 36.000s 11.061us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 39.000s 13.320us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 37.000s 10.438us 9 10 90.00
tl_intg_err 30 30 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
otbn_tl_intg_err 60.000s 196.776us 25 25 100.00
passthru_mem_tl_intg_err 4 5 80.00
otbn_passthru_mem_tl_intg_err 51.000s 415.733us 4 5 80.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 68.000s 163.304us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 41.000s 19.188us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 42.000s 21.056us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 60.000s 196.776us 25 25 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 39.000s 27.533us 59 60 98.33
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 42.000s 21.056us 10 10 100.00
otbn_dmem_err 41.000s 19.188us 15 15 100.00
otbn_zero_state_err_urnd 34.000s 61.326us 5 5 100.00
otbn_illegal_mem_acc 36.000s 11.061us 5 5 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
sec_cm_scramble_key_sideload 99 100 99.00
otbn_single 50.000s 97.996us 99 100 99.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 42.000s 21.056us 10 10 100.00
otbn_dmem_err 41.000s 19.188us 15 15 100.00
otbn_zero_state_err_urnd 34.000s 61.326us 5 5 100.00
otbn_illegal_mem_acc 36.000s 11.061us 5 5 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 39.000s 27.533us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 42.000s 21.056us 10 10 100.00
otbn_dmem_err 41.000s 19.188us 15 15 100.00
otbn_zero_state_err_urnd 34.000s 61.326us 5 5 100.00
otbn_illegal_mem_acc 36.000s 11.061us 5 5 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
sec_cm_data_reg_sw_sca 99 100 99.00
otbn_single 50.000s 97.996us 99 100 99.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 37.000s 64.416us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 39.000s 45.141us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 110.000s 418.214us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 110.000s 418.214us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 9 10 90.00
otbn_rf_base_intg_err 40.000s 22.118us 9 10 90.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 8 10 80.00
otbn_rf_bignum_intg_err 39.000s 224.757us 8 10 80.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 40.000s 26.008us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 40.000s 26.008us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 46.000s 46.023us 7 7 100.00
sec_cm_data_mem_sec_wipe 99 100 99.00
otbn_single 50.000s 97.996us 99 100 99.00
sec_cm_instruction_mem_sec_wipe 99 100 99.00
otbn_single 50.000s 97.996us 99 100 99.00
sec_cm_data_reg_sw_sec_wipe 99 100 99.00
otbn_single 50.000s 97.996us 99 100 99.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 172.000s 469.819us 10 10 100.00
sec_cm_ctrl_flow_count 99 100 99.00
otbn_single 50.000s 97.996us 99 100 99.00
sec_cm_ctrl_flow_sca 99 100 99.00
otbn_single 50.000s 97.996us 99 100 99.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 36.000s 17.614us 5 5 100.00
sec_cm_key_sideload 99 100 99.00
otbn_single 50.000s 97.996us 99 100 99.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 322.000s 4902.577us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
otbn_stress_all_with_rand_reset 317.000s 1753.725us 5 10 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 37.000s 79.469us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 5 test runs
otbn_alu_bignum_mod_err 18524170689785101767559147554043351379484119352305264637551938542516293098648 133
UVM_INFO @ 83028107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_controller_ispr_rdata_err 448275961561433511626056473383235320918326584427367835066972687953936012589 147
UVM_INFO @ 157010160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_mac_bignum_acc_err 62249614596130056573053895745063778250967628431546932036911145987841520015254 118
UVM_INFO @ 73449283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 9384446972545319055020586300754843212859050534403729225172360283892775130827 120
UVM_INFO @ 30171965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 15731543753704226719559207381031450307515378782663998672718237356535137685381 118
UVM_INFO @ 102353059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
otbn_stress_all_with_rand_reset 5863454940159066180866674737187548859653973950927873547987497996261720107082 275
UVM_INFO @ 893412933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 47019799109618149878955437873483411635054767466613107093473610325027032695013 158
UVM_INFO @ 451568298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 96538248758968529488251982011902943613228474232676440356295981527471475362600 353
UVM_INFO @ 566080579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 4268517527295970990603356384087263416932188306724965320711291338138788712094 239
UVM_INFO @ 989967922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 112810550102283987015154517287666730254611070734757160303878654887574686291669 253
UVM_INFO @ 42392761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 56708435971101880366836985545799840025640901974330587093493002383674093026117 91
UVM_INFO @ 13938746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:217) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr otbn_reg_block.cmd (addr=*) 1 test run
otbn_rf_base_intg_err 88762676575783138790471308557076133935007236451414233172788376701912729408583 115
UVM_INFO @ 2087719378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 85984515667604463711406776943299622538108552685158038621463362791044563076945 147
UVM_INFO @ 7826108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 93182581002921703017921885097857745629661756483696093804127642237636758195294 120
UVM_ERROR @ 10957600 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 10957600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,161): Assertion IdleIfLockedAndNotRotatingKeys_A has failed (* cycles, starting * PS) 1 test run
otbn_partial_wipe 74671792237100973753290265029848978503950326672827132346590205568336348811109 130
UVM_ERROR @ 4343546 ps: (otbn_idle_checker.sv:161) [ASSERT FAILED] IdleIfLockedAndNotRotatingKeys_A
UVM_INFO @ 4343546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_single 46901376101862382344950223531787797733035255802621854167665870863286075481498 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_base_vseq.sv:486) [otbn_dmem_err_vseq] Timed out waiting for OTBN run to complete 1 test run
otbn_stress_all 29462703359654691030296524738377277226808374199847348625436461361813213057297 148
UVM_INFO @ 10010750001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_escalate 70788365187457727908577541072316045174070547783767902092690918911685026332151 108
UVM_INFO @ 12234936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---