Simulation Results: otp_ctrl

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.20 %
  • code
  • 86.19 %
  • assert
  • 94.75 %
  • func
  • 92.67 %
  • line
  • 90.38 %
  • branch
  • 86.85 %
  • cond
  • 94.02 %
  • toggle
  • 95.79 %
  • FSM
  • 63.89 %
Validation stages
V1
92.31%
V2
96.48%
V2S
96.06%
V3
23.76%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.470s 204.361us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 15.140s 1220.548us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.140s 94.890us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.840s 698.681us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.290s 83.297us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.680s 270.818us 1 1 100.00
csr_mem_rw_with_rand_reset 3 5 60.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.670s 107.772us 3 5 60.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.840s 698.681us 5 5 100.00
otp_ctrl_csr_aliasing 5.680s 270.818us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.330s 39.825us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.440s 568.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 15.540s 1220.752us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 8.670s 2577.170us 300 300 100.00
partition_check 37 60 61.67
otp_ctrl_background_chks 28.570s 4402.672us 10 10 100.00
otp_ctrl_check_fail 36.050s 4361.192us 27 50 54.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 14.710s 5418.428us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 42.200s 6978.222us 30 30 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 35.890s 4381.135us 10 10 100.00
lc_interactions 210 210 100.00
otp_ctrl_parallel_lc_req 20.540s 11889.946us 10 10 100.00
otp_ctrl_parallel_lc_esc 37.340s 15016.327us 200 200 100.00
otp_dai_errors 10 10 100.00
otp_ctrl_dai_errs 27.200s 1407.450us 10 10 100.00
otp_macro_errors 7 10 70.00
otp_ctrl_macro_errs 22.570s 3559.482us 7 10 70.00
test_access 10 10 100.00
otp_ctrl_test_access 58.480s 32859.646us 10 10 100.00
stress_all 10 10 100.00
otp_ctrl_stress_all 243.310s 31309.053us 10 10 100.00
intr_test 10 10 100.00
otp_ctrl_intr_test 2.670s 573.067us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 2.660s 902.889us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 10.610s 3567.803us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 10.610s 3567.803us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.140s 94.890us 1 1 100.00
otp_ctrl_csr_rw 2.840s 698.681us 5 5 100.00
otp_ctrl_csr_aliasing 5.680s 270.818us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.590s 129.974us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.140s 94.890us 1 1 100.00
otp_ctrl_csr_rw 2.840s 698.681us 5 5 100.00
otp_ctrl_csr_aliasing 5.680s 270.818us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.590s 129.974us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
otp_ctrl_tl_intg_err 32.540s 20201.200us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 32.540s 20201.200us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 15.140s 1220.548us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 15.140s 1220.548us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_dai_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 37.340s 15016.327us 200 200 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 37.340s 15016.327us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 37.340s 15016.327us 200 200 100.00
sec_cm_part_fsm_local_esc 207 210 98.57
otp_ctrl_parallel_lc_esc 37.340s 15016.327us 200 200 100.00
otp_ctrl_macro_errs 22.570s 3559.482us 7 10 70.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 37.340s 15016.327us 200 200 100.00
sec_cm_timer_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 37.340s 15016.327us 200 200 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_dai_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 37.340s 15016.327us 200 200 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 37.340s 15016.327us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 37.340s 15016.327us 200 200 100.00
sec_cm_part_fsm_global_esc 207 210 98.57
otp_ctrl_parallel_lc_esc 37.340s 15016.327us 200 200 100.00
otp_ctrl_macro_errs 22.570s 3559.482us 7 10 70.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 37.340s 15016.327us 200 200 100.00
sec_cm_timer_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 37.340s 15016.327us 200 200 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 8.670s 2577.170us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 27 50 54.00
otp_ctrl_check_fail 36.050s 4361.192us 27 50 54.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 42.200s 6978.222us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 42.200s 6978.222us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 42.200s 6978.222us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 42.200s 6978.222us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 42.200s 6978.222us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 15.140s 1220.548us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 42.200s 6978.222us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 15.140s 1220.548us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 266.080s 155555.217us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 14.710s 5418.428us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 15.140s 1220.548us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 15.140s 1220.548us 10 10 100.00
sec_cm_macro_mem_integrity 7 10 70.00
otp_ctrl_macro_errs 22.570s 3559.482us 7 10 70.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 16.130s 7638.291us 1 1 100.00
stress_all_with_rand_reset 23 100 23.00
otp_ctrl_stress_all_with_rand_reset 2285.560s 1410761.646us 23 100 23.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 38 test runs
otp_ctrl_macro_errs 6460760227306134715098492892862124347302891297213192279624927518296681513699 9554
UVM_INFO @ 499386560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 98390020228993247199467297867831218827952168230600313971796421535450552292514 23058
UVM_INFO @ 2812091742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 64243424489799770432804454805861186166569878969788946706699993347396891634070 399
UVM_INFO @ 116295129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53861468113026770281934428455413398552996037816549853331137199929463978109263 817
UVM_INFO @ 264001022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 47585085366627653892784756237651880411635521412400577694152680060976416995595 4790
UVM_INFO @ 1767226669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 104335260410281511525649360316171733088179767595418279432193134557017022723708 4140
UVM_INFO @ 2491576304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 90810242759401291349863402091587276642433758622100448882022834187141884874668 4522
UVM_INFO @ 123484568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 52551410512129546974259254771626627635677890223201416117686109166455077170131 3646
UVM_INFO @ 710627274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 9751350222696955297547869235972301552224495346855184891178630056290637844792 3291
UVM_INFO @ 351656633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 48384357726608667564865620726433354687605360512371512447224044533973788101366 6558
UVM_INFO @ 778439857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 82831099418693953819222109378828267513409473374998615260950525065300591877705 141
UVM_INFO @ 145670914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 34940536851746946957412594343572527388027117122103321548369249658125767643902 855
UVM_INFO @ 223293856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 4596535738015194962401078087146359701623374313306943394219962927429070798639 6501
UVM_INFO @ 811141731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 111989592844826133843842982729595835723187755110977236467080127512645530319712 3425
UVM_INFO @ 496154441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 4326815336287645747442069278483981330025383941546467845914832531121432160257 797
UVM_INFO @ 1262123935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35614645332028170448443535792778293363805691372786508069450029933735862485314 7734
UVM_INFO @ 1624315732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 6664080576161931589612356870507784796364341622080350312481269682713396804540 1693
UVM_INFO @ 63898321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 89280404785707225655839247801797352469102249096463860573985810140014632158672 4128
UVM_INFO @ 187684339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 110749190681777424599372772811793313371963173100956282425608314378847784953534 6506
UVM_INFO @ 1474637327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74046867329542918469066540689650547983770174983874968370188659467694223563742 147
UVM_INFO @ 629119037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 30449987895799118048906712239392274020629534811376958193764978527290294784618 14498
UVM_INFO @ 1177788604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 85298954478041100000361307074046370177066913271670994429237901654119507038666 18154
UVM_INFO @ 11993038752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 59662445642532491648885276423854992159043643696790337731866395448341018428107 4076
UVM_INFO @ 423165932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 66364178627188543766324419373809314201494528541372944145688745957731334742918 271
UVM_INFO @ 212284347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 109973506230179179864392869702756270267246896129982303971838017914406700407951 7141
UVM_INFO @ 4062270829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 42653906756233446845002626034417303968260081611167146138387661824087389506025 8753
UVM_INFO @ 3504986357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 17532803961744863321323341314031607412535250011110192991304238054588277517591 2566
UVM_INFO @ 254250268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 94909623395340193788472547839247620863995030589226084829891813964404687052287 3074
UVM_INFO @ 475922809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 76793243245556229265658035273366240288099137470745338910275701087668566158886 111
UVM_INFO @ 56678132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73784626811198614482176929072708874157673159961565819488575487543881778798540 14193
UVM_INFO @ 736971870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12589824753379095905105970189020176502859431084218105736351575225641544116484 11372
UVM_INFO @ 5047440631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28124931487511611600064092603782054937282362012587003326673997432703281163097 196
UVM_INFO @ 1791844059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89578251737982558266790232646399668857354268520276307093469895194143916938004 856
UVM_INFO @ 253108230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 49596828282676829364744316721149939529248028831051836298234898860979156609775 263
UVM_INFO @ 79628102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51636616007137282821704565105158174463690203774753375564560975519564056720859 2525
UVM_INFO @ 3228523122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32361214345428720549047545138732198941435767551136559969444944172723873115422 2343
UVM_INFO @ 249477244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 49530805634466286576574205305139742073359393104424847854999572144338618489340 13804
UVM_INFO @ 1620023053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7713178774448943270010720709177453392468801182213503911576097645919001846493 2292
UVM_INFO @ 10427686501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 30 test runs
otp_ctrl_stress_all_with_rand_reset 38967627073672774257062375054536541711782282369146866900673121529194051974444 10382
UVM_INFO @ 10998920108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53121663005756909299949232783475480794203556377380431810228581654615972451962 9470
UVM_INFO @ 1053659394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 115608755504465287031676569016703064187894624091071305403750299513463461112558 4234
UVM_INFO @ 4557633019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39442469510949279322894628389115732965915354189490574999152116364704572460771 15249
UVM_INFO @ 4665240979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18593315786386898275887531195297502119319029514788599064253475678527696224680 239
UVM_INFO @ 1460477193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33062970089046033758438417815916824277854241224361654769431900121550292652777 4188
UVM_INFO @ 343917732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72481496774205374554510098351836306329313788386841910800795387821995248370565 10268
UVM_INFO @ 1491142946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 49961129166241161666572968990991012670424993049764574354990048971369950890329 4605
UVM_INFO @ 2347678576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34419386660502436821907772876175489749031323175635883490641708680390551200579 92
UVM_INFO @ 108153392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 98112094569006016276066112390322722330975050225733196867357314671592754005487 4577
UVM_INFO @ 4597142119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 16104003646699083254620466786935298068890998827619422290447585325661504798285 2563
UVM_INFO @ 11990055427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35321534032657487110357305078560380947583867351358562605197664857519446273600 2768
UVM_INFO @ 7745320875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9032468448175380932750098639476108431409479343644052930692747194192294402388 92
UVM_INFO @ 58997525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84064381671919720872587941564026611298288758891463382839293805603415767478360 1346
UVM_INFO @ 2067451357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51325729297154864840708250998217012773685964710675078481770789843573280425173 11258
UVM_INFO @ 449825875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35420139442523860470395976130332687984967176946289271191562042677566078631871 7139
UVM_INFO @ 437673747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35859009258833711423506881607205238625286193299373065698476131734418853782811 92
UVM_INFO @ 48704898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23355757590361792566582399968428126125718370665652486171847655215714639473559 2899
UVM_INFO @ 1989809954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5107262203823189478367929112911943865762585608781154614437702825164462664839 25062
UVM_INFO @ 6800473265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 87500062537050155477633601485596845633390472729409523234151460219319865616704 93
UVM_INFO @ 41138134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 57332996811731092776735708091177856610122403088706715047909421772690347862636 27646
UVM_INFO @ 4300577722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26159290598208812054467714713501686362233013079315802756667651192118426096310 41223
UVM_INFO @ 9521013417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41105870496062581353632504577411531993022065768708762434815250377904122000433 2418
UVM_INFO @ 557162446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 8394771291955116779340055274227184268164299805939750791070336428076970838020 20608
UVM_INFO @ 4859188005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 14662723070692164556307934504610979758708104465841864927099102689109121848757 147
UVM_INFO @ 989593377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109412103889245503336789294281040365425244863869012274414769348715285012216561 92
UVM_INFO @ 53257243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109691265650792944142720482540037996909045760437283089445000295104979595876645 5536
UVM_INFO @ 466706899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44454211623099340242228314292776363393254757448554476963600311753226564255343 3124
UVM_INFO @ 7509906054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84596633457284130895227971683094439975698994399117135841129235746693890839229 92
UVM_INFO @ 26991586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41868133881805181723980065201379776331486908248585853294190971377886364322666 10548
UVM_INFO @ 7898634566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 17 test runs
otp_ctrl_stress_all_with_rand_reset 12209901684132171343802898806160994055653287796650183289649471289084239607446 169
UVM_INFO @ 32433733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43734931281357298012583600205912888223315881697312893196794292306574116920243 388
UVM_INFO @ 239119542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54585440705722378621383770910532905850951913489636772227162607404279527850247 9333
UVM_INFO @ 2633372357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34065616307267952434607989120117779806246152155383810992690295693256540608534 9122
UVM_INFO @ 24184403464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26505884184937105451396454443544062780127230712909214351915314989166011828293 3402
UVM_INFO @ 2143344446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 67816302214088573697190485717289773613960974431536772827300107110266522918458 953
UVM_INFO @ 2436200192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4595854541952830288644736040368151581398084776391079721118063185389734479796 10819
UVM_INFO @ 18561983112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10985235818930191685788644780789758425302069021997474940853258614957139083942 5742
UVM_INFO @ 1210607950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 110136954454710372899765388393794955431216225185782368664453391335486611331261 14439
UVM_INFO @ 32376595106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79102520279325024969972694747538522816673749214149774464342129078152189465668 13336
UVM_INFO @ 55108618176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72275124677375013601301545299998821262726182926154425226491642142805074914276 3879
UVM_INFO @ 8215212255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106243765846841288549432423872299873884343905072681575337249023408935380518965 14743
UVM_INFO @ 1583468869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 20296926849447923319637375070482301554681772570086876995091932310928138719910 315
UVM_INFO @ 561659205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4859251278031339485722362255280742816592045571189824843412451223819915099071 2206
UVM_INFO @ 6507987688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25940570438968992720494865846473350030908546796568173291408406741138084232322 8680
UVM_INFO @ 1713055397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 71534838397033457187570759304275503190268565070325788023094822272268120307943 18926
UVM_INFO @ 2412550000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65781425714885191701726796249488674367948937373460263022797716765983130369950 7355
UVM_INFO @ 12705015476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 15 test runs
otp_ctrl_stress_all_with_rand_reset 14528372989574230923841585445396326318941752755158796772681272694997647677268 179
UVM_INFO @ 62753822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 38196063210870125406160863903349428797598369520437613818564132930787366811217 92
UVM_INFO @ 103040648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56800266194289924867156648183008814467619737753891660001422328671761253524936 1519
UVM_INFO @ 933568762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 67761144051750194380963778636774446119396400767172641922087370404552478057660 92
UVM_INFO @ 27073652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75635666901651897118654459125698842970283963386823021709593501267381316136987 3097
UVM_INFO @ 11356990553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18768269258296108556851278321691175930309347997988420782597729907249758949288 320
UVM_INFO @ 175123168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84336072460986139432452734100793927754215764743895218632926873671589589944637 178
UVM_INFO @ 55503167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45018022290718714252867790353583866195428016985491072562581691455337062144379 44074
UVM_INFO @ 4152167633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96954289678793371557610974520281001544169684218815663213034531285118380138935 236
UVM_INFO @ 16868303165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65186673393361962059039854138602324963400439785030267267863627912642313441727 14676
UVM_INFO @ 5478568818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74651601788144628511724454420735862918266954791932883979942149736385231174922 5036
UVM_INFO @ 1757571806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 94340618413990733501955264355650431787673701824178420093302863446525011963954 92
UVM_INFO @ 69602464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62364779108622631667420680850394077554820717624298123098148612697449539821783 2942
UVM_INFO @ 1842047247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99105309129032800714275972393039714401255925185252609036166816219676260289436 17134
UVM_INFO @ 1544796535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 71311031119758770951228152115740188930247173093100475732264495799075951388959 92
UVM_INFO @ 53315069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:205) [scoreboard] Check failed cfg.otp_ctrl_vif.lc_data_o.error == exp_lc_data.error (* [*] vs * [*]) 1 test run
otp_ctrl_stress_all_with_rand_reset 50216981033851278780010695604324505859304817852193344455627841369114716521234 16843
UVM_INFO @ 3562993017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 8400704960404080543267994972303343262145358248499793591798267347067768358457 184
UVM_INFO @ 6193319764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 1 test run
otp_ctrl_stress_all_with_rand_reset 86143061266607334192237960765330720493887294905591946386781425332429685784758 7663
UVM_ERROR @ 16296515545 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 16296515545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 34316178436606127968968145209003210911374479052591014579482454763928979270562 189
UVM_INFO @ 18790416584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_stress_all_with_rand_reset 87093976694745644809932988614900278355555585652390700183666884951110954837416 1563
UVM_INFO @ 1410761646369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---