| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| pwm_smoke | 5.000s | 513.303us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| pwm_csr_hw_reset | 1.000s | 18.061us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| pwm_csr_rw | 2.000s | 18.963us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| pwm_csr_bit_bash | 7.000s | 486.533us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| pwm_csr_aliasing | 2.000s | 23.625us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| pwm_csr_mem_rw_with_rand_reset | 2.000s | 26.607us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| pwm_csr_rw | 2.000s | 18.963us | 5 | 5 | 100.00 | |
| pwm_csr_aliasing | 2.000s | 23.625us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dutycycle | 25 | 25 | 100.00 | |||
| pwm_rand_output | 75.000s | 43749.699us | 25 | 25 | 100.00 | |
| pulse | 25 | 25 | 100.00 | |||
| pwm_rand_output | 75.000s | 43749.699us | 25 | 25 | 100.00 | |
| blink | 25 | 25 | 100.00 | |||
| pwm_rand_output | 75.000s | 43749.699us | 25 | 25 | 100.00 | |
| heartbeat | 25 | 25 | 100.00 | |||
| pwm_rand_output | 75.000s | 43749.699us | 25 | 25 | 100.00 | |
| resolution | 25 | 25 | 100.00 | |||
| pwm_rand_output | 75.000s | 43749.699us | 25 | 25 | 100.00 | |
| multi_channel | 25 | 25 | 100.00 | |||
| pwm_rand_output | 75.000s | 43749.699us | 25 | 25 | 100.00 | |
| polarity | 25 | 25 | 100.00 | |||
| pwm_rand_output | 75.000s | 43749.699us | 25 | 25 | 100.00 | |
| phase | 50 | 50 | 100.00 | |||
| pwm_rand_output | 75.000s | 43749.699us | 25 | 25 | 100.00 | |
| pwm_phase | 80.000s | 10499.971us | 25 | 25 | 100.00 | |
| lowpower | 25 | 25 | 100.00 | |||
| pwm_rand_output | 75.000s | 43749.699us | 25 | 25 | 100.00 | |
| perf | 10 | 10 | 100.00 | |||
| pwm_perf | 63.000s | 20999.331us | 10 | 10 | 100.00 | |
| regwen | 1 | 1 | 100.00 | |||
| pwm_regwen | 158.000s | 10507.991us | 1 | 1 | 100.00 | |
| stress_all | 25 | 25 | 100.00 | |||
| pwm_stress_all | 225.000s | 92845.006us | 25 | 25 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| pwm_alert_test | 2.000s | 13.917us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| pwm_tl_errors | 4.000s | 78.098us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| pwm_tl_errors | 4.000s | 78.098us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| pwm_csr_hw_reset | 1.000s | 18.061us | 1 | 1 | 100.00 | |
| pwm_csr_rw | 2.000s | 18.963us | 5 | 5 | 100.00 | |
| pwm_csr_aliasing | 2.000s | 23.625us | 1 | 1 | 100.00 | |
| pwm_same_csr_outstanding | 3.000s | 216.232us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| pwm_csr_hw_reset | 1.000s | 18.061us | 1 | 1 | 100.00 | |
| pwm_csr_rw | 2.000s | 18.963us | 5 | 5 | 100.00 | |
| pwm_csr_aliasing | 2.000s | 23.625us | 1 | 1 | 100.00 | |
| pwm_same_csr_outstanding | 3.000s | 216.232us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| pwm_tl_intg_err | 4.000s | 533.168us | 25 | 25 | 100.00 | |
| pwm_sec_cm | 2.000s | 164.881us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| pwm_tl_intg_err | 4.000s | 533.168us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| heartbeat_wrap | 10 | 10 | 100.00 | |||
| pwm_heartbeat_wrap | 83.000s | 21880.980us | 10 | 10 | 100.00 | |