| V1 |
|
100.00% |
| V2 |
|
89.05% |
| V2S |
|
71.43% |
| V3 |
|
65.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| pwrmgr_smoke | 0.980s | 36.451us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| pwrmgr_csr_hw_reset | 1.060s | 30.964us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| pwrmgr_csr_rw | 1.070s | 22.733us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| pwrmgr_csr_bit_bash | 2.300s | 229.813us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| pwrmgr_csr_aliasing | 1.350s | 167.327us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| pwrmgr_csr_mem_rw_with_rand_reset | 2.120s | 60.672us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| pwrmgr_csr_rw | 1.070s | 22.733us | 5 | 5 | 100.00 | |
| pwrmgr_csr_aliasing | 1.350s | 167.327us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wakeup | 10 | 10 | 100.00 | |||
| pwrmgr_wakeup | 1.640s | 198.523us | 10 | 10 | 100.00 | |
| control_clks | 10 | 10 | 100.00 | |||
| pwrmgr_wakeup | 1.640s | 198.523us | 10 | 10 | 100.00 | |
| aborted_low_power | 20 | 20 | 100.00 | |||
| pwrmgr_aborted_low_power | 1.240s | 85.425us | 10 | 10 | 100.00 | |
| pwrmgr_lowpower_invalid | 1.090s | 53.927us | 10 | 10 | 100.00 | |
| reset | 12 | 20 | 60.00 | |||
| pwrmgr_reset | 4.210s | 1000.000us | 5 | 10 | 50.00 | |
| pwrmgr_reset_invalid | 1.170s | 111.169us | 7 | 10 | 70.00 | |
| main_power_glitch_reset | 5 | 10 | 50.00 | |||
| pwrmgr_reset | 4.210s | 1000.000us | 5 | 10 | 50.00 | |
| reset_wakeup_race | 10 | 10 | 100.00 | |||
| pwrmgr_wakeup_reset | 1.860s | 304.610us | 10 | 10 | 100.00 | |
| lowpower_wakeup_race | 10 | 10 | 100.00 | |||
| pwrmgr_lowpower_wakeup_race | 1.210s | 132.730us | 10 | 10 | 100.00 | |
| disable_rom_integrity_check | 6 | 10 | 60.00 | |||
| pwrmgr_disable_rom_integrity_check | 2.570s | 1000.000us | 6 | 10 | 60.00 | |
| stress_all | 7 | 10 | 70.00 | |||
| pwrmgr_stress_all | 9.280s | 2515.175us | 7 | 10 | 70.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| pwrmgr_intr_test | 0.990s | 20.135us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| pwrmgr_tl_errors | 2.410s | 827.326us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| pwrmgr_tl_errors | 2.410s | 827.326us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| pwrmgr_csr_hw_reset | 1.060s | 30.964us | 1 | 1 | 100.00 | |
| pwrmgr_csr_rw | 1.070s | 22.733us | 5 | 5 | 100.00 | |
| pwrmgr_csr_aliasing | 1.350s | 167.327us | 1 | 1 | 100.00 | |
| pwrmgr_same_csr_outstanding | 1.150s | 77.397us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| pwrmgr_csr_hw_reset | 1.060s | 30.964us | 1 | 1 | 100.00 | |
| pwrmgr_csr_rw | 1.070s | 22.733us | 5 | 5 | 100.00 | |
| pwrmgr_csr_aliasing | 1.350s | 167.327us | 1 | 1 | 100.00 | |
| pwrmgr_same_csr_outstanding | 1.150s | 77.397us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 30 | 0.00 | |||
| pwrmgr_tl_intg_err | 0.990s | 7.886us | 0 | 25 | 0.00 | |
| pwrmgr_sec_cm | 1.150s | 36.480us | 0 | 5 | 0.00 | |
| prim_count_check | 0 | 5 | 0.00 | |||
| pwrmgr_sec_cm | 1.150s | 36.480us | 0 | 5 | 0.00 | |
| prim_fsm_check | 0 | 5 | 0.00 | |||
| pwrmgr_sec_cm | 1.150s | 36.480us | 0 | 5 | 0.00 | |
| sec_cm_bus_integrity | 0 | 25 | 0.00 | |||
| pwrmgr_tl_intg_err | 0.990s | 7.886us | 0 | 25 | 0.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 10 | 10 | 100.00 | |||
| pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 3.160s | 784.067us | 10 | 10 | 100.00 | |
| sec_cm_rom_ctrl_intersig_mubi | 10 | 10 | 100.00 | |||
| pwrmgr_wakeup_reset | 1.860s | 304.610us | 10 | 10 | 100.00 | |
| sec_cm_rstmgr_intersig_mubi | 10 | 10 | 100.00 | |||
| pwrmgr_sec_cm_rstmgr_intersig_mubi | 1.140s | 46.930us | 10 | 10 | 100.00 | |
| sec_cm_esc_rx_clk_bkgn_chk | 10 | 10 | 100.00 | |||
| pwrmgr_esc_clk_rst_malfunc | 0.940s | 31.925us | 10 | 10 | 100.00 | |
| sec_cm_esc_rx_clk_local_esc | 0 | 5 | 0.00 | |||
| pwrmgr_sec_cm | 1.150s | 36.480us | 0 | 5 | 0.00 | |
| sec_cm_fsm_sparse | 0 | 5 | 0.00 | |||
| pwrmgr_sec_cm | 1.150s | 36.480us | 0 | 5 | 0.00 | |
| sec_cm_fsm_terminal | 0 | 5 | 0.00 | |||
| pwrmgr_sec_cm | 1.150s | 36.480us | 0 | 5 | 0.00 | |
| sec_cm_ctrl_flow_global_esc | 10 | 10 | 100.00 | |||
| pwrmgr_global_esc | 1.000s | 49.176us | 10 | 10 | 100.00 | |
| sec_cm_main_pd_rst_local_esc | 10 | 10 | 100.00 | |||
| pwrmgr_glitch | 1.070s | 61.413us | 10 | 10 | 100.00 | |
| sec_cm_ctrl_config_regwen | 10 | 10 | 100.00 | |||
| pwrmgr_sec_cm_ctrl_config_regwen | 1.260s | 62.039us | 10 | 10 | 100.00 | |
| sec_cm_wakeup_config_regwen | 5 | 5 | 100.00 | |||
| pwrmgr_csr_rw | 1.070s | 22.733us | 5 | 5 | 100.00 | |
| sec_cm_reset_config_regwen | 5 | 5 | 100.00 | |||
| pwrmgr_csr_rw | 1.070s | 22.733us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| escalation_timeout | 4 | 10 | 40.00 | |||
| pwrmgr_escalation_timeout | 1.320s | 108.894us | 4 | 10 | 40.00 | |
| stress_all_with_rand_reset | 9 | 10 | 90.00 | |||
| pwrmgr_stress_all_with_rand_reset | 10.480s | 4154.714us | 9 | 10 | 90.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire | 30 test runs | |||
| pwrmgr_tl_intg_err | 98409395777297980072480494081452346546625715276034478369613853196273769664364 | 85 |
UVM_INFO @ 10343981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_sec_cm | 86433796804481745016866757737741444617821968174172441218782926500020383277848 | 85 |
UVM_INFO @ 36480196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 57573542853952528874826579796688225636698376012657655570819480765882206814029 | 85 |
UVM_INFO @ 7974394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_sec_cm | 8638974097601122390088347569774792058410538136993529857536579759638930975271 | 85 |
UVM_INFO @ 30476527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 68955848282322363028227310843671393812920298329129289356055534177831007742530 | 85 |
UVM_INFO @ 12075471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_sec_cm | 70294776482005364965029216415991520796575877108311500290748578373358854732205 | 81 |
UVM_INFO @ 27523634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 102148933197681099210435152769380233059285641400919520162732970419392570535778 | 82 |
UVM_INFO @ 7806314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_sec_cm | 90321606714366670364074394203817266247824753293540346957833023219261414282826 | 82 |
UVM_INFO @ 19219939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 1046480784679589680983503662406581530112401171138320421580997610690167727998 | 85 |
UVM_INFO @ 17674423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_sec_cm | 22760045182995509395476965506247907264866031424914834315504380924057845566241 | 78 |
UVM_INFO @ 7609253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 24254018745851920809601823467701942502013375028497682546206897249374308201376 | 78 |
UVM_INFO @ 36786868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 82274169593200169242187204821669735388213515312577065533837946390209789769450 | 82 |
UVM_INFO @ 11599723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 65908506378645193561664598297020036916735371724290528940118319806684789520022 | 82 |
UVM_INFO @ 8166441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 86870825336064503522063987698263583468742523798417950076418422518282207741310 | 78 |
UVM_INFO @ 10402857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 89317476218041218495520848170329752701396410803803222343972897055768069450967 | 85 |
UVM_INFO @ 14019906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 47541324384499292124553850912545015069242462518915262685349742508452634145505 | 85 |
UVM_INFO @ 14989626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 37734664640219906544646101071917252736513526519139874264630949934298432716917 | 85 |
UVM_INFO @ 10757199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 89907992993987034428989368947027995841045034829876136008496976353725436177872 | 82 |
UVM_INFO @ 7490675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 8957483177663557910054161994668680049854443592456160836452195269234655044272 | 82 |
UVM_INFO @ 11878645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 40850652770582474340550799872873304991185561840416582215542702636043797417438 | 82 |
UVM_INFO @ 10461434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 9158943461969973664890191288138072488946416843720626217756800375160800247663 | 82 |
UVM_INFO @ 9299868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 83720064579812828368034361415366216972975879735731534686470970570947835163308 | 82 |
UVM_INFO @ 7886331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 13484426570386331102386355662327082123846748212785740629522610358150183049431 | 85 |
UVM_INFO @ 7700210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 91960123324463653228273239898610537214155507546757884080569511455499973311690 | 82 |
UVM_INFO @ 25096497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 27324432446134655267924071741115631027874639217784809760006135889267989023374 | 78 |
UVM_INFO @ 13324376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 112571946671633290589810697675842271281277681322939256210007251815114512244089 | 85 |
UVM_INFO @ 7778339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 78489754291806103589265481664921930489635285865461366473416784928997990813459 | 78 |
UVM_INFO @ 16548607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 81021974815138227800388645514249078176205911386478634668250703785530525626949 | 78 |
UVM_INFO @ 8531428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 86952283339243664474145457208572246625480389378060118803641960481426965922711 | 78 |
UVM_INFO @ 10140174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_tl_intg_err | 72059931171334122245384505156470761542380125494664764592507139628887507819429 | 85 |
UVM_INFO @ 8861439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 9 test runs | |||
| pwrmgr_reset | 59654022322889385682015380094985419346920974600530573011977299280213981442954 | 160 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset | 84874435542136431475611612467892223825341457081295036488231356549218473748885 | 139 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_disable_rom_integrity_check | 29729348160780716262654596864759135075738077056313110576554702789926009110121 | 107 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset | 9795867395652374022180804277409377889861783142317909102306983705008669330547 | 116 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset | 113207873394742402695713516416523374451225041913880571097456958770827168354976 | 91 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_disable_rom_integrity_check | 67634067750552947921205417136352310987079439624051676484435327176901993221498 | 109 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_disable_rom_integrity_check | 26301723436705664648523253376460544730422728483346693639926416011593089734034 | 106 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset | 468576416018206717019126168701472632622222099507657826455415570785411198366 | 97 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_disable_rom_integrity_check | 4683417457928335249216853858943858460280543346564578350370818122992338656575 | 140 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((!clk_en) || status)' | 6 test runs | |||
| pwrmgr_escalation_timeout | 17542566579126864953374720037914152951020541632970384868338916309594945091465 | 79 |
UVM_ERROR @ 732803240 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 732803240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 92111781369334276595199732866283302738268734416357034840586694570241753013701 | 79 |
UVM_ERROR @ 102583454 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 102583454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 21875021822365576367063851551373458883251664189923258492534901947038690054821 | 79 |
UVM_ERROR @ 97822363 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 97822363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 99721117041413235916338581674290867828928754346395941392270437406373579731861 | 79 |
UVM_ERROR @ 136110703 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 136110703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 8231131242672482383421034980837873193719652808351100244158880983928256511651 | 79 |
UVM_ERROR @ 102328365 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 102328365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 111071997215667303190465726078445526077192955809361454729081579046070040208259 | 79 |
UVM_ERROR @ 100520763 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 100520763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! | 3 test runs | |||
| pwrmgr_stress_all | 19797474209728268030464092093643045458629686778064306638239448542814409333473 | 336 |
UVM_INFO @ 10902480355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 18634887477412191534563015067311820341862731653009793728126259661752492842785 | 1109 |
UVM_INFO @ 12399453282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 48897509032621072368685796240135097471178774488885107581588937840912571833538 | 176 |
UVM_INFO @ 10172071367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitNvmShutDown | 1 test run | |||
| pwrmgr_reset_invalid | 106061018012813603203088887511041676844324777039850002832601030868373086849010 | 107 |
UVM_INFO @ 34669809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitReleaseLcRst | 1 test run | |||
| pwrmgr_reset_invalid | 114106110001259219851113950543226355053073187505212246523328641013557710187377 | 128 |
UVM_INFO @ 79205660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:454) [pwrmgr_common_vseq] wait timeout occurred! | 1 test run | |||
| pwrmgr_stress_all_with_rand_reset | 48890922899140209243501209705901999961735921252103268076411277445564598641325 | 623 |
UVM_INFO @ 10583560309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitOtpInit | 1 test run | |||
| pwrmgr_reset_invalid | 61051480769108512941589907143921489506203480520349096015685295307435727123982 | 115 |
UVM_INFO @ 73335519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|