Simulation Results: rom_ctrl/32kb

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.61%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.200s 5041.501us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.660s 1014.084us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 4.430s 593.147us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.440s 170.953us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.150s 555.209us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.640s 179.417us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 4.430s 593.147us 5 5 100.00
rom_ctrl_csr_aliasing 4.150s 555.209us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.190s 123.672us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.710s 123.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.840s 229.353us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 28.680s 3761.876us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 8.670s 565.708us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 8.120s 648.546us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 12.120s 1087.647us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 12.120s 1087.647us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.660s 1014.084us 1 1 100.00
rom_ctrl_csr_rw 4.430s 593.147us 5 5 100.00
rom_ctrl_csr_aliasing 4.150s 555.209us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.120s 558.380us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.660s 1014.084us 1 1 100.00
rom_ctrl_csr_rw 4.430s 593.147us 5 5 100.00
rom_ctrl_csr_aliasing 4.150s 555.209us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.120s 558.380us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 129.650s 3675.639us 18 20 90.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.760s 3303.147us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 312.550s 598.275us 5 5 100.00
rom_ctrl_tl_intg_err 75.610s 2948.158us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 312.550s 598.275us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 312.550s 598.275us 5 5 100.00
sec_cm_checker_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 129.650s 3675.639us 18 20 90.00
sec_cm_checker_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 129.650s 3675.639us 18 20 90.00
sec_cm_checker_fsm_local_esc 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 129.650s 3675.639us 18 20 90.00
sec_cm_compare_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 129.650s 3675.639us 18 20 90.00
sec_cm_compare_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 129.650s 3675.639us 18 20 90.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 312.550s 598.275us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 312.550s 598.275us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.200s 5041.501us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.200s 5041.501us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.200s 5041.501us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 75.610s 2948.158us 25 25 100.00
sec_cm_bus_local_esc 20 22 90.91
rom_ctrl_corrupt_sig_fatal_chk 129.650s 3675.639us 18 20 90.00
rom_ctrl_kmac_err_chk 8.670s 565.708us 2 2 100.00
sec_cm_mux_mubi 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 129.650s 3675.639us 18 20 90.00
sec_cm_mux_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 129.650s 3675.639us 18 20 90.00
sec_cm_ctrl_redun 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 129.650s 3675.639us 18 20 90.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.760s 3303.147us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 312.550s 598.275us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 403.330s 4423.948us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 53577360646282303974800430465327326731127160431283759453409246298950023666604 85
UVM_INFO @ 1406452583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 66538359204907785169420564566469258356251751387715998626238021726838140901603 86
UVM_INFO @ 545769277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---