Simulation Results: rom_ctrl/64kb

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 13.460s 302.590us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 13.710s 227.259us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 12.340s 375.272us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 10.520s 989.304us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.610s 954.915us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 15.800s 19934.643us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 12.340s 375.272us 5 5 100.00
rom_ctrl_csr_aliasing 6.610s 954.915us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.110s 533.448us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.680s 410.323us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 10.010s 306.276us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 55.600s 1110.929us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 18.540s 394.562us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 12.200s 535.327us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 20.340s 7628.985us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 20.340s 7628.985us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 13.710s 227.259us 1 1 100.00
rom_ctrl_csr_rw 12.340s 375.272us 5 5 100.00
rom_ctrl_csr_aliasing 6.610s 954.915us 1 1 100.00
rom_ctrl_same_csr_outstanding 11.120s 286.709us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 13.710s 227.259us 1 1 100.00
rom_ctrl_csr_rw 12.340s 375.272us 5 5 100.00
rom_ctrl_csr_aliasing 6.610s 954.915us 1 1 100.00
rom_ctrl_same_csr_outstanding 11.120s 286.709us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 342.940s 34345.257us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 47.950s 1107.556us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 551.410s 2865.558us 5 5 100.00
rom_ctrl_tl_intg_err 162.150s 876.782us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 551.410s 2865.558us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 551.410s 2865.558us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 342.940s 34345.257us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 342.940s 34345.257us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 342.940s 34345.257us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 342.940s 34345.257us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 342.940s 34345.257us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 551.410s 2865.558us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 551.410s 2865.558us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 13.460s 302.590us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 13.460s 302.590us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 13.460s 302.590us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 162.150s 876.782us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 342.940s 34345.257us 20 20 100.00
rom_ctrl_kmac_err_chk 18.540s 394.562us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 342.940s 34345.257us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 342.940s 34345.257us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 342.940s 34345.257us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 47.950s 1107.556us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 551.410s 2865.558us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 350.730s 15209.444us 20 20 100.00