Simulation Results: rstmgr

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.86 %
  • code
  • 99.68 %
  • assert
  • 98.13 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.38 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
rstmgr_smoke 1.750s 260.124us 5 5 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.140s 93.742us 1 1 100.00
csr_rw 5 5 100.00
rstmgr_csr_rw 1.290s 74.581us 5 5 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 11.500s 2300.083us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.810s 113.406us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.100s 224.484us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rstmgr_csr_rw 1.290s 74.581us 5 5 100.00
rstmgr_csr_aliasing 1.810s 113.406us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 5 5 100.00
rstmgr_por_stretcher 1.310s 230.694us 5 5 100.00
sw_rst 5 5 100.00
rstmgr_sw_rst 2.740s 359.537us 5 5 100.00
sw_rst_reset_race 5 5 100.00
rstmgr_sw_rst_reset_race 1.770s 240.457us 5 5 100.00
reset_info 5 5 100.00
rstmgr_reset 6.690s 1610.992us 5 5 100.00
cpu_info 5 5 100.00
rstmgr_reset 6.690s 1610.992us 5 5 100.00
alert_info 5 5 100.00
rstmgr_reset 6.690s 1610.992us 5 5 100.00
reset_info_capture 5 5 100.00
rstmgr_reset 6.690s 1610.992us 5 5 100.00
stress_all 5 5 100.00
rstmgr_stress_all 33.050s 9865.578us 5 5 100.00
alert_test 10 10 100.00
rstmgr_alert_test 1.280s 99.483us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rstmgr_tl_errors 3.980s 496.526us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rstmgr_tl_errors 3.980s 496.526us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rstmgr_csr_hw_reset 1.140s 93.742us 1 1 100.00
rstmgr_csr_rw 1.290s 74.581us 5 5 100.00
rstmgr_csr_aliasing 1.810s 113.406us 1 1 100.00
rstmgr_same_csr_outstanding 1.920s 202.444us 5 5 100.00
tl_d_partial_access 12 12 100.00
rstmgr_csr_hw_reset 1.140s 93.742us 1 1 100.00
rstmgr_csr_rw 1.290s 74.581us 5 5 100.00
rstmgr_csr_aliasing 1.810s 113.406us 1 1 100.00
rstmgr_same_csr_outstanding 1.920s 202.444us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rstmgr_sec_cm 26.290s 16824.500us 5 5 100.00
rstmgr_tl_intg_err 4.450s 1013.239us 25 25 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 26.290s 16824.500us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 26.290s 16824.500us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
rstmgr_tl_intg_err 4.450s 1013.239us 25 25 100.00
sec_cm_scan_intersig_mubi 5 5 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.590s 149.569us 5 5 100.00
sec_cm_leaf_rst_bkgn_chk 25 25 100.00
rstmgr_leaf_rst_cnsty 11.000s 2457.840us 25 25 100.00
sec_cm_leaf_rst_shadow 5 5 100.00
rstmgr_leaf_rst_shadow_attack 1.730s 301.530us 5 5 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 26.290s 16824.500us 5 5 100.00
sec_cm_sw_rst_config_regwen 5 5 100.00
rstmgr_csr_rw 1.290s 74.581us 5 5 100.00
sec_cm_dump_ctrl_config_regwen 5 5 100.00
rstmgr_csr_rw 1.290s 74.581us 5 5 100.00