| V1 |
|
100.00% |
| V2 |
|
85.04% |
| V2S |
|
100.00% |
| V3 |
|
45.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 2.020s | 533.348us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.890s | 46.358us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rv_timer_csr_rw | 0.900s | 14.182us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 3.490s | 552.000us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 1.080s | 36.997us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.760s | 81.108us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rv_timer_csr_rw | 0.900s | 14.182us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.080s | 36.997us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 1 | 20 | 5.00 | |||
| rv_timer_random_reset | 12.770s | 35624.670us | 1 | 20 | 5.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 5.700s | 3648.794us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 651.620s | 3270999.117us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 651.620s | 3270999.117us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 21.760s | 11914.334us | 20 | 20 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rv_timer_alert_test | 0.850s | 18.465us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| rv_timer_intr_test | 0.910s | 12.807us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.040s | 864.635us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.040s | 864.635us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.890s | 46.358us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.900s | 14.182us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.080s | 36.997us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.030s | 29.393us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.890s | 46.358us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.900s | 14.182us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.080s | 36.997us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.030s | 29.393us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rv_timer_sec_cm | 1.270s | 131.039us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.800s | 1158.360us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.800s | 1158.360us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 2 | 10 | 20.00 | |||
| rv_timer_min | 2.510s | 116.524us | 2 | 10 | 20.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.170s | 43.709us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 16 | 20 | 80.00 | |||
| rv_timer_stress_all_with_rand_reset | 56.500s | 51484.378us | 16 | 20 | 80.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 27 test runs | |||
| rv_timer_min | 104031857101936593727442479376732236003006639404328978242936452684058083917421 | 76 |
UVM_INFO @ 335149377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 89910101851579433541436789533031075193947551877553303202024740693856592222328 | 75 |
UVM_INFO @ 23715961142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 90305312227763119914457903275646837686439547348620996948420212156271924191447 | 76 |
UVM_INFO @ 740255084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 43738645560206278935470790248233194287002778923467543036427090310775297911246 | 75 |
UVM_INFO @ 1586051393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 19497012853954837317365830387889378126222531405735307746997273928204436338952 | 78 |
UVM_INFO @ 217120726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 104155608061603555416243744844052970354240726067865330512778084547089897050619 | 75 |
UVM_INFO @ 35624669992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 63838540865357282920252641566990746000847526660989989794759523764026077903381 | 77 |
UVM_INFO @ 792577803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 71489993166401935204821295412690435683351251277057507418798311569068204403158 | 75 |
UVM_INFO @ 116524120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 44916131403049738938966187438229788308654272138541001298820077971695785978628 | 75 |
UVM_INFO @ 291738815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 90322906703071952019980812587844275711521259526742984401659933883393725314240 | 75 |
UVM_INFO @ 382894530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 94677243238430313968191985636008784013068202387141873523550008189266687312728 | 75 |
UVM_INFO @ 119001696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 105844055675628699618676556925789911673600849000496708523421549881378449839272 | 75 |
UVM_INFO @ 507304884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 110461276447452156802312080245850247052639318571419165143023567751882153061420 | 75 |
UVM_INFO @ 115401726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 69347978566877719138170416829579931213892620355383417110177459162913772965100 | 75 |
UVM_INFO @ 1023960337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 100285434095151716835900937279960076720835603602222910311877410809466792777058 | 79 |
UVM_INFO @ 337434779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 90129850539109715344793926917938909544632151409391200198195981910426511978412 | 75 |
UVM_INFO @ 545907746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 85379689565796862090001324164616440330256838082859720531167971499088585435062 | 75 |
UVM_INFO @ 10821697852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 45108550469627313125923591313230619404013188216905350621754239623373638321645 | 76 |
UVM_INFO @ 89691892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 28376028908747528441646724430673639304021011701504075203361790776129912542523 | 75 |
UVM_INFO @ 107441113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 92493914060989242072454976748146941783909126323667262640061750001777413511085 | 75 |
UVM_INFO @ 3084212592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 40157606333369213482295271371184708667552156727227421222133289702447437318557 | 75 |
UVM_INFO @ 274042233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 87648080120057512071443483778017338262656705182530174550613009714241087262055 | 75 |
UVM_INFO @ 61494662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 106850727780337478230164840962851731753344741642730904083165869608670002327673 | 75 |
UVM_INFO @ 562504549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 72076092586348875898245584619934314775314056994921671992377758017942376412014 | 75 |
UVM_INFO @ 222741096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 73860396182567058726204669971279898967788211374902526262579805660751343617850 | 76 |
UVM_INFO @ 1855838266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 115002632401799003872266205997503360795879006143653428445534018275952659596477 | 75 |
UVM_INFO @ 159099079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 32348131072610727394451087213745502197252662308578521288290703089378639494852 | 75 |
UVM_INFO @ 18471238370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 10 test runs | |||
| rv_timer_max | 31242292101644053289863884977321298649833917911057230877378914552252906440584 | 75 |
UVM_INFO @ 385442260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 74098076603746804177119866014929913728812621673059513949907882385736226383776 | 76 |
UVM_INFO @ 51468671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 51284869794379425459675044128667518775081165032661212189052035073706051999486 | 75 |
UVM_INFO @ 93523524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 100483974879051054562938851997777281213096715540524781444626282404820030332265 | 75 |
UVM_INFO @ 47802786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 111898974057547947779290870622311478657701596066980489688903136894488536820505 | 75 |
UVM_INFO @ 43709426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 113043335479214706723875856518926071860024875997940335796581915847658110497188 | 75 |
UVM_INFO @ 156623899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 83884303616217228926004009462039148880976094179702383851759703756530068617340 | 76 |
UVM_INFO @ 50469993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 47825103247943766399644428586663400597809215209949207267063333214733762952599 | 75 |
UVM_INFO @ 62946439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 68425191884472310926256006334573358335108376343606572327394711057086348537135 | 75 |
UVM_INFO @ 237375336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 89312607612205656018207834347266519532859140947748658096740103857618392342582 | 75 |
UVM_INFO @ 86455519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) | 2 test runs | |||
| rv_timer_stress_all_with_rand_reset | 31863323022157514148168695147101801315282497276725464811259084417851293205669 | 291 |
UVM_INFO @ 14855708448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 61327715346564578127749422537991750347834881528865519942472048625163466853290 | 526 |
UVM_INFO @ 51484378498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 2 test runs | |||
| rv_timer_stress_all_with_rand_reset | 7046003451627052231580626683813747761077795228342003624619821672357230098319 | 91 |
UVM_INFO @ 18982264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 27319988745242524665135193488429476686128661187952130134190257508790864330696 | 489 |
UVM_INFO @ 48099622480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|