Simulation Results: spi_host

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.83 %
  • code
  • 95.08 %
  • assert
  • 95.64 %
  • func
  • 90.76 %
  • block
  • 97.05 %
  • line
  • 98.76 %
  • branch
  • 93.55 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 88.000s 7575.151us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 29.848us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 17.560us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 245.087us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 108.470us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 59.668us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 17.560us 5 5 100.00
spi_host_csr_aliasing 2.000s 108.470us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 19.812us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 38.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 56.625us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 13.000s 1162.738us 10 10 100.00
spi_host_error_cmd 2.000s 46.346us 10 10 100.00
spi_host_event 564.000s 18890.703us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 5.000s 342.233us 10 10 100.00
speed 10 10 100.00
spi_host_speed 5.000s 342.233us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 5.000s 342.233us 10 10 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 112.000s 5953.400us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 29.148us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 5.000s 342.233us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 5.000s 342.233us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 88.000s 7575.151us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 88.000s 7575.151us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 76.000s 11444.751us 10 10 100.00
spien 10 10 100.00
spi_host_spien 19.000s 650.700us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 171.000s 4987.452us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 3.000s 1067.395us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 13.000s 1162.738us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 39.782us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 54.230us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 264.946us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 264.946us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 29.848us 1 1 100.00
spi_host_csr_rw 2.000s 17.560us 5 5 100.00
spi_host_csr_aliasing 2.000s 108.470us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 81.730us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 29.848us 1 1 100.00
spi_host_csr_rw 2.000s 17.560us 5 5 100.00
spi_host_csr_aliasing 2.000s 108.470us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 81.730us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 98.964us 25 25 100.00
spi_host_sec_cm 2.000s 236.292us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 98.964us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 5 5 100.00
spi_host_upper_range_clkdiv 596.000s 44399.826us 5 5 100.00