Simulation Results: uart

 
21/05/2026 15:00:32 DVSim: v1.38.0 sha: e92b798 json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.77 %
  • code
  • 96.86 %
  • assert
  • 97.12 %
  • func
  • 99.32 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.25 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.73%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
uart_smoke 9.350s 5692.832us 10 10 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.900s 30.010us 1 1 100.00
csr_rw 5 5 100.00
uart_csr_rw 0.980s 13.082us 5 5 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.580s 56.852us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 26.621us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
uart_csr_mem_rw_with_rand_reset 1.660s 149.073us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
uart_csr_rw 0.980s 13.082us 5 5 100.00
uart_csr_aliasing 1.000s 26.621us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 10 10 100.00
uart_tx_rx 102.380s 178032.992us 10 10 100.00
parity 20 20 100.00
uart_smoke 9.350s 5692.832us 10 10 100.00
uart_tx_rx 102.380s 178032.992us 10 10 100.00
parity_error 20 20 100.00
uart_intr 124.090s 91681.218us 10 10 100.00
uart_rx_parity_err 142.630s 92390.357us 10 10 100.00
watermark 20 20 100.00
uart_tx_rx 102.380s 178032.992us 10 10 100.00
uart_intr 124.090s 91681.218us 10 10 100.00
fifo_full 10 10 100.00
uart_fifo_full 472.620s 120856.637us 10 10 100.00
fifo_overflow 10 10 100.00
uart_fifo_overflow 175.760s 125079.393us 10 10 100.00
fifo_reset 200 200 100.00
uart_fifo_reset 391.530s 173871.990us 200 200 100.00
rx_frame_err 10 10 100.00
uart_intr 124.090s 91681.218us 10 10 100.00
rx_break_err 10 10 100.00
uart_intr 124.090s 91681.218us 10 10 100.00
rx_timeout 10 10 100.00
uart_intr 124.090s 91681.218us 10 10 100.00
perf 10 10 100.00
uart_perf 767.430s 20506.679us 10 10 100.00
sys_loopback 10 10 100.00
uart_loopback 9.980s 3204.287us 10 10 100.00
line_loopback 10 10 100.00
uart_loopback 9.980s 3204.287us 10 10 100.00
rx_noise_filter 1 10 10.00
uart_noise_filter 71.570s 71148.096us 1 10 10.00
rx_start_bit_filter 10 10 100.00
uart_rx_start_bit_filter 8.030s 5244.024us 10 10 100.00
tx_overide 10 10 100.00
uart_tx_ovrd 23.000s 7065.129us 10 10 100.00
rx_oversample 10 10 100.00
uart_rx_oversample 24.120s 4338.211us 10 10 100.00
long_b2b_transfer 10 10 100.00
uart_long_xfer_wo_dly 954.880s 144372.502us 10 10 100.00
stress_all 10 10 100.00
uart_stress_all 508.870s 261236.037us 10 10 100.00
alert_test 10 10 100.00
uart_alert_test 0.930s 12.070us 10 10 100.00
intr_test 10 10 100.00
uart_intr_test 0.940s 27.427us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
uart_tl_errors 2.830s 416.989us 25 25 100.00
tl_d_illegal_access 25 25 100.00
uart_tl_errors 2.830s 416.989us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
uart_csr_hw_reset 0.900s 30.010us 1 1 100.00
uart_csr_rw 0.980s 13.082us 5 5 100.00
uart_csr_aliasing 1.000s 26.621us 1 1 100.00
uart_same_csr_outstanding 1.140s 51.335us 5 5 100.00
tl_d_partial_access 12 12 100.00
uart_csr_hw_reset 0.900s 30.010us 1 1 100.00
uart_csr_rw 0.980s 13.082us 5 5 100.00
uart_csr_aliasing 1.000s 26.621us 1 1 100.00
uart_same_csr_outstanding 1.140s 51.335us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
uart_sec_cm 1.330s 110.320us 5 5 100.00
uart_tl_intg_err 2.050s 451.923us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
uart_tl_intg_err 2.050s 451.923us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
uart_stress_all_with_rand_reset 104.830s 30988.962us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 8 test runs
uart_noise_filter 115075340016640091506496515051107374713572099708192524688360121202547528069410 77
UVM_ERROR @ 5593529375 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5593987723 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5594904419 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5595362767 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 42538973601252996626276086387204272264897715374726705848029634553910032031538 82
UVM_ERROR @ 63194040093 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 63194040093 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 63201040149 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 63288452613 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 20, clk_pulses: 0
uart_noise_filter 24850104554315249840466598773457135335975643670810580606500059223343451926000 74
UVM_ERROR @ 197691712 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 197691712 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 197691712 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 241858202 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 39699273271802929251589131321259678774998324425765664945820174817010626887295 78
UVM_ERROR @ 10223080836 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 10226835908 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 10288763984 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 10289070104 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 86946532184703640299665827757734258982814479103128575785189397343438991925001 75
UVM_ERROR @ 3402358181 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3404646779 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3405203465 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3406193129 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all_with_rand_reset 68829561763227509997465526667397975281941522269944438138499696060999667842127 131
UVM_INFO @ 8750380308 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 8750700308 ps: (cip_base_vseq.sv:1173) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Stress w/ reset is done for run 4/10
uart_stress_all_with_rand_reset 6001000244250364057671547306296900548546327970045462857115890545186581515702 130
UVM_ERROR @ 2204881725 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 2220453029 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/987
UVM_ERROR @ 2293207549 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 2293207549 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 509152762385818488215522997889044908098430064482846395324894712714638040529 77
UVM_ERROR @ 2609740416 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 2621720416 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 2621720416 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2760400416 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 3 test runs
uart_noise_filter 15705321398632831178789825223155930398896303553638664769014503363256641631409 83
UVM_ERROR @ 69871433444 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 69871447333 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (145 [0x91] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 69989823280 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 69989837169 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_noise_filter 68838009251852191696372540408523347984631188870232506538617073162407748606277 75
UVM_ERROR @ 1105965442 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1106005442 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60 [0x3c] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1185405442 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 1305005442 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
uart_noise_filter 6041300920987335709666085496434846440969339017373607714965053752754143746071 78
UVM_ERROR @ 9311780851 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 9311800851 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (194 [0xc2] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 9347160851 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 9347160851 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1