Simulation Results

Simulation Results: adc_ctrl

24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
67.00 %

code
95.61 %

assert
91.73 %

func
13.66 %

line
98.83 %

branch
97.34 %

cond
87.55 %

toggle
99.76 %

FSM
94.59 %

Validation stages

V1		100.00%
V2		50.85%
V2S		100.00%
V3		0.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	adc_ctrl_smoke	20.920s	5854.798us	10	10	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	4.150s	1260.381us	1	1	100.00
csr_rw				5	5	100.00
	adc_ctrl_csr_rw	2.370s	540.804us	5	5	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	29.000s	28746.355us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	3.220s	559.743us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.980s	365.116us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	adc_ctrl_csr_rw	2.370s	540.804us	5	5	100.00
	adc_ctrl_csr_aliasing	3.220s	559.743us	1	1	100.00

90/177 passed

50.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	10	0.00
	adc_ctrl_filters_polled	2.620s	502.720us	0	10	0.00
filters_polled_fixed				0	10	0.00
	adc_ctrl_filters_polled_fixed	2.270s	503.587us	0	10	0.00
filters_interrupt				0	10	0.00
	adc_ctrl_filters_interrupt	2.010s	357.904us	0	10	0.00
filters_interrupt_fixed				0	10	0.00
	adc_ctrl_filters_interrupt_fixed	2.670s	520.569us	0	10	0.00
filters_wakeup				0	10	0.00
	adc_ctrl_filters_wakeup	2.360s	526.293us	0	10	0.00
filters_wakeup_fixed				0	10	0.00
	adc_ctrl_filters_wakeup_fixed	2.360s	444.556us	0	10	0.00
filters_both				0	10	0.00
	adc_ctrl_filters_both	2.490s	491.727us	0	10	0.00
clock_gating				0	10	0.00
	adc_ctrl_clock_gating	2.500s	503.729us	0	10	0.00
poweron_counter				10	10	100.00
	adc_ctrl_poweron_counter	17.930s	5027.711us	10	10	100.00
lowpower_counter				10	10	100.00
	adc_ctrl_lowpower_counter	105.960s	40845.598us	10	10	100.00
fsm_reset				10	10	100.00
	adc_ctrl_fsm_reset	270.540s	131339.893us	10	10	100.00
stress_all				3	10	30.00
	adc_ctrl_stress_all	88.600s	49163.687us	3	10	30.00
alert_test				10	10	100.00
	adc_ctrl_alert_test	1.990s	381.659us	10	10	100.00
intr_test				10	10	100.00
	adc_ctrl_intr_test	2.400s	435.903us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	adc_ctrl_tl_errors	4.390s	547.313us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	adc_ctrl_tl_errors	4.390s	547.313us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	adc_ctrl_csr_hw_reset	4.150s	1260.381us	1	1	100.00
	adc_ctrl_csr_rw	2.370s	540.804us	5	5	100.00
	adc_ctrl_csr_aliasing	3.220s	559.743us	1	1	100.00
	adc_ctrl_same_csr_outstanding	9.360s	2152.420us	5	5	100.00
tl_d_partial_access				12	12	100.00
	adc_ctrl_csr_hw_reset	4.150s	1260.381us	1	1	100.00
	adc_ctrl_csr_rw	2.370s	540.804us	5	5	100.00
	adc_ctrl_csr_aliasing	3.220s	559.743us	1	1	100.00
	adc_ctrl_same_csr_outstanding	9.360s	2152.420us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	adc_ctrl_sec_cm	10.680s	3698.330us	5	5	100.00
	adc_ctrl_tl_intg_err	28.420s	8578.107us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	adc_ctrl_tl_intg_err	28.420s	8578.107us	25	25	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	adc_ctrl_stress_all_with_rand_reset	13.020s	2208.554us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				97 test runs
	adc_ctrl_filters_polled	85890498763055058342971994223346391011700302190370002389154227073469175671149	388	UVM_INFO @ 502719813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	35614139032199615865463421076840392365973882981106727863713714204368839880239	388	UVM_INFO @ 425084104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	13371794273503245615044822869337902248283595679379873274889658913647010352669	388	UVM_INFO @ 357904043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	24174629406945474835996372881064659010565041282296064842069880927389675748798	388	UVM_INFO @ 526300331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	71887341658833484925132623199364895928684621960201554748191803489733053464633	388	UVM_INFO @ 358746575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	58072055281726916468991536784967625740030361771157925985864402421426040824145	388	UVM_INFO @ 352179078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	112775205749625920996356620512713003021326938283719891344227350679811585116277	388	UVM_INFO @ 503729362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	47910537721741764459470109055858307069654497812589711726225647640378557704007	388	UVM_INFO @ 377183163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	77716428700284027806824526775324470119302426957779114755935089110541727685958	408	UVM_INFO @ 1022676931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	76450514776468288427716150254819003312355179322957599661311442972801191337258	389	UVM_INFO @ 765035722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	28924519154569097929164009400339905618474297921775037360242511030584651678952	388	UVM_INFO @ 358985242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	53872563895039783504211047322566806410978700670301366671731257301172841917054	388	UVM_INFO @ 337000112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	80096529170448882230238708348200750604610216969931973915090618039348774853348	388	UVM_INFO @ 315304931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	1860211279518484162512099373102514716890170530081162929652845540451967996465	388	UVM_INFO @ 383435694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	88183185904091677685885337781435060887137302153654365287531322047026558749352	388	UVM_INFO @ 421908769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	67425223890482428957629188329879083649543925943300825823567046814304456491074	388	UVM_INFO @ 309475301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	74322651583963624928160229385951375276496507944019025641802696552160676102062	388	UVM_INFO @ 501391456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	59627944416218391513021432060072610781697334967759011349134164335311198176969	388	UVM_INFO @ 491726964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	1929525612800265327731718598004019312019497936674510298517202282315635356973	394	UVM_INFO @ 662403226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	64211449124684856219263806146125252110727077655706125298217543786171838928021	389	UVM_INFO @ 936550852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	35530272354198971515131246863333784544274081739664889176674393412018759681287	388	UVM_INFO @ 332354018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	63392139452701604989384507523428048276700070757915112982635815003000222486754	388	UVM_INFO @ 373903465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	8569448046767038105137544156014883179561166093132898030722456935038912587592	388	UVM_INFO @ 373875223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	107511990369450269568352633138557375760243191757192399897994019992603146437334	388	UVM_INFO @ 484036922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	89783749217310074995080296243279014265878895106074200487574938360681354036832	388	UVM_INFO @ 311622365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	91703595024271412595939375910132510354294641846373590343769941410556373085522	388	UVM_INFO @ 485662790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	44214518888480296202120646461227949071030658167085837288315640748348663514153	388	UVM_INFO @ 479578446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	71160432564177141530677835659753815147653545312591537474397353483122078544607	388	UVM_INFO @ 296116554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	81192561430273828360840835102715338382662415235995080088530430803256163245493	394	UVM_INFO @ 569038439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	70144704891192018689493150459782736174831821179370720659957130890079222641263	389	UVM_INFO @ 858959237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	79253029042553584367487901218429661755291345277343831099981589114126814836980	388	UVM_INFO @ 484615527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	33371118950504569556790418787673528987622099341469483899588991202357407448664	388	UVM_INFO @ 407655469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	47836414047673403179607986133804216435471878752063108960447811598618916921370	388	UVM_INFO @ 401694097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	76507220587964674172024330806514075025745680548196098161830028961828573759195	388	UVM_INFO @ 360920652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	86172428848512781582221957939082195424539664105070942224539858428089710283568	388	UVM_INFO @ 396526426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	16812601654870721690420491268225800955947314156328064867735467809913662164067	388	UVM_INFO @ 354270973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	111692889088539021445232578755501103320972720341463711161886335121232543417705	388	UVM_INFO @ 358892016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	115607574506392802187688655767500403446183790217537731253575617643168875127928	388	UVM_INFO @ 421534606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	37113399347211177407427025031296896280407323486065418007863344600762479342006	394	UVM_INFO @ 803348345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	99789562363454804876548582356588811345595098401225350771113437778248973944720	388	UVM_INFO @ 473747802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	12833053984796146136226026872670951684290194604543475108092244187342696406546	388	UVM_INFO @ 355985384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	64931075201713091405849129428017252149822834696597964169918238007291444560207	388	UVM_INFO @ 520253237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	73111432623802617538210475585376809658362834426537529283597414605899886045520	388	UVM_INFO @ 306357356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	108377720805522013378169162543499274707152180261255903912930839688094716288719	388	UVM_INFO @ 362842194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	103613331095642852433729536786998252517885909456806753129871913568616514659425	388	UVM_INFO @ 444555780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	114779313273578329083427356389506546408421039262007367272647312311529209513672	388	UVM_INFO @ 377554416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	1909448679523119408791805666615493049835061894786603935876105707909363449383	388	UVM_INFO @ 284109318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	1513676317532096506304372034430133567654001180961958227545923195166306699668	421	UVM_INFO @ 2728948965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	39029883210606678779958784781017099581989244750956469110060257896838954358696	388	UVM_INFO @ 404336375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	63205376018571046560392222875310156408124811100202872324553908826425838356087	388	UVM_INFO @ 480718632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	26181725530876271119822775980977630730904087344298587777918048979843516798491	388	UVM_INFO @ 328943462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	22647090325200897068131171017422861564378390324488924053523764977988674575423	388	UVM_INFO @ 375688332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	47674110856795962226878475054464599753964245358790714501703559364370078387890	388	UVM_INFO @ 379555930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	31195046910004020591339960102190685009369251650854677205701007392274065899005	388	UVM_INFO @ 359448710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	109258876674392292840067545861544283700727366945909901825661408899822662973750	388	UVM_INFO @ 334628725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	28566365764829325643489412801670007821585279273427138051359735959273179595615	388	UVM_INFO @ 357907610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	4581741321308991513659846649283592401704312386337531190996894659741144507538	401	UVM_INFO @ 836844013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	100956782112243733787122407113562360044101883695839952634056306678819324014784	388	UVM_INFO @ 491402894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	32673798461737877807510326616584089382539374669379676157520847150239077101161	388	UVM_INFO @ 357548500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	75830219404778848307397908288019437921460716382645545329103895415102896065044	388	UVM_INFO @ 405761069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	93144907166900030149518849399096852287491233452395674303841910053415183698159	388	UVM_INFO @ 458839310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	44980446339463782886710146215095333615543685786709470316680987418461158224679	388	UVM_INFO @ 356112859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	110201800765201308797259909457318965879795988234429912613151997860603018166356	388	UVM_INFO @ 414250197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	14749104134700757894567267957288022042601291672938496564181114657664652130846	388	UVM_INFO @ 324040982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	58749471290548327110328204983516722278705672164270866438188650055477129488340	388	UVM_INFO @ 473392175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	66500945722581123339112617143425798187494454097743135224020271064228709468986	421	UVM_INFO @ 1386048152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	43737101681799183633333004878788155010994670605678833561140101296335693661953	389	UVM_INFO @ 767851007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	7423013284128270152123623035402873370903404588038974964874258437495391138609	388	UVM_INFO @ 377759802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	104203277898561015954719618652872988754522287232910202899757522650026243927190	388	UVM_INFO @ 460331823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	16540643437134929338966255552220364167067302489353741764457777024002862182211	388	UVM_INFO @ 423634946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	2509454411615610068372053574148770049913667175042794402982215789198804978051	388	UVM_INFO @ 335898826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	54899569802272719363991158540073484261709427421761039501673399118889063501750	388	UVM_INFO @ 281733298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	95853799701111150377384271305686590447750265402611733492035121954687600676671	388	UVM_INFO @ 346875292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	60490888418538797031448631669591869753232091985048295603096372989797846008735	388	UVM_INFO @ 450947726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	112233288813653244615326388379368883083604422052787556648555881276070376183253	388	UVM_INFO @ 276014071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	30934861020297208616410122694808673043969208113968348677337065403602197369314	401	UVM_INFO @ 874436195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	89793676873043558105158108770385659990023275619812676623809219328395973454583	389	UVM_INFO @ 778776792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	16411974240564508855495893243569020600860278567920492254945922315690255063061	388	UVM_INFO @ 395670494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	25861956263723108606108064313706927000703299017771575200337454736460887483715	388	UVM_INFO @ 430918133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	68611012374536505531001633327035802077773868595791992958954375232917857116351	388	UVM_INFO @ 360635368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	31856567142353118560045163654034588473892561815080646315474571583917357677516	388	UVM_INFO @ 520568695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	49409858605288203534606502311411882231856269002093856180608166938027883900280	388	UVM_INFO @ 526293429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	15769190522356970877036179639605228339050534717454988685531361806764818763555	388	UVM_INFO @ 492467285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	114381257967409971047552874659107499173918018172640352033456828285327490339264	388	UVM_INFO @ 359954329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	71680477699587565069950975715034995557914491142050564092175057322396790611596	388	UVM_INFO @ 458959351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	25240698603057490526886387662514390260624533696454169182082054201074780788407	447	UVM_INFO @ 2208554259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	304139832592191212494717327807046477945430403624362091105327434938439584629	451	UVM_INFO @ 23120083499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	18931543357184734508782094379816446245091171628500001422408330126692567124251	388	UVM_INFO @ 359181618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	55065170564253589876095009573780703929466499357614002415078874246204516146198	388	UVM_INFO @ 503587277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	75616535854122961468109360552341524521857171091016501610117647353559368783061	388	UVM_INFO @ 312456384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	103793849097587581068090604300863033491387026114318644592818741587650125400860	388	UVM_INFO @ 472124087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	65059604486708677109115489390299189580381829812734530252151246302450901953900	388	UVM_INFO @ 317940649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	90300883779436856628389758649689430947016266862191522720319146258227448122676	388	UVM_INFO @ 410021331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	95333151574372340126530884029157427811127402619836193763928886963521912746961	388	UVM_INFO @ 393905544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	50583587548566171177251454992888228710558363827468219029863121295349916154684	388	UVM_INFO @ 373057264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	17176776514932019719590537099161764805094806056557710434673153776949980658206	411	UVM_INFO @ 1132778015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	65033286615204211286169152191379294454759015458517107036686952300402221279094	493	UVM_INFO @ 49163686985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---