Simulation Results: aes/masked

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.75 %
  • code
  • 96.61 %
  • assert
  • 98.38 %
  • func
  • 98.26 %
  • block
  • 96.98 %
  • line
  • 98.05 %
  • branch
  • 92.63 %
  • toggle
  • 97.99 %
  • FSM
  • 97.78 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.71%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 201.909us 1 1 100.00
smoke 10 10 100.00
aes_smoke 9.000s 244.525us 10 10 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 15.000s 84.995us 1 1 100.00
csr_rw 5 5 100.00
aes_csr_rw 3.000s 139.277us 5 5 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 26.000s 390.396us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 24.000s 159.067us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 89.140us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
aes_csr_rw 3.000s 139.277us 5 5 100.00
aes_csr_aliasing 24.000s 159.067us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 70 70 100.00
aes_smoke 9.000s 244.525us 10 10 100.00
aes_config_error 32.000s 762.371us 50 50 100.00
aes_stress 26.000s 961.342us 10 10 100.00
key_length 70 70 100.00
aes_smoke 9.000s 244.525us 10 10 100.00
aes_config_error 32.000s 762.371us 50 50 100.00
aes_stress 26.000s 961.342us 10 10 100.00
back2back 35 35 100.00
aes_stress 26.000s 961.342us 10 10 100.00
aes_b2b 57.000s 835.633us 25 25 100.00
backpressure 10 10 100.00
aes_stress 26.000s 961.342us 10 10 100.00
multi_message 95 95 100.00
aes_smoke 9.000s 244.525us 10 10 100.00
aes_config_error 32.000s 762.371us 50 50 100.00
aes_stress 26.000s 961.342us 10 10 100.00
aes_alert_reset 30.000s 102.928us 25 25 100.00
failure_test 85 85 100.00
aes_man_cfg_err 4.000s 88.514us 10 10 100.00
aes_config_error 32.000s 762.371us 50 50 100.00
aes_alert_reset 30.000s 102.928us 25 25 100.00
trigger_clear_test 10 10 100.00
aes_clear 30.000s 189.428us 10 10 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 13.000s 220.237us 1 1 100.00
reset_recovery 25 25 100.00
aes_alert_reset 30.000s 102.928us 25 25 100.00
stress 10 10 100.00
aes_stress 26.000s 961.342us 10 10 100.00
sideload 20 20 100.00
aes_stress 26.000s 961.342us 10 10 100.00
aes_sideload 38.000s 1261.383us 10 10 100.00
deinitialization 10 10 100.00
aes_deinit 7.000s 214.570us 10 10 100.00
stress_all 10 10 100.00
aes_stress_all 117.000s 4981.838us 10 10 100.00
alert_test 10 10 100.00
aes_alert_test 28.000s 99.383us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
aes_tl_errors 5.000s 187.168us 25 25 100.00
tl_d_illegal_access 25 25 100.00
aes_tl_errors 5.000s 187.168us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
aes_csr_hw_reset 15.000s 84.995us 1 1 100.00
aes_csr_rw 3.000s 139.277us 5 5 100.00
aes_csr_aliasing 24.000s 159.067us 1 1 100.00
aes_same_csr_outstanding 3.000s 139.540us 5 5 100.00
tl_d_partial_access 12 12 100.00
aes_csr_hw_reset 15.000s 84.995us 1 1 100.00
aes_csr_rw 3.000s 139.277us 5 5 100.00
aes_csr_aliasing 24.000s 159.067us 1 1 100.00
aes_same_csr_outstanding 3.000s 139.540us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 10 10 100.00
aes_reseed 8.000s 214.337us 10 10 100.00
fault_inject 627 660 95.00
aes_fi 6.000s 111.129us 10 10 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 57.000s 10005.074us 340 350 97.14
shadow_reg_update_error 18 20 90.00
aes_shadow_reg_errors 26.000s 10026.576us 18 20 90.00
shadow_reg_read_clear_staged_value 18 20 90.00
aes_shadow_reg_errors 26.000s 10026.576us 18 20 90.00
shadow_reg_storage_error 18 20 90.00
aes_shadow_reg_errors 26.000s 10026.576us 18 20 90.00
shadowed_reset_glitch 18 20 90.00
aes_shadow_reg_errors 26.000s 10026.576us 18 20 90.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 150.626us 20 20 100.00
tl_intg_err 30 30 100.00
aes_sec_cm 6.000s 1384.670us 5 5 100.00
aes_tl_intg_err 5.000s 802.562us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
aes_tl_intg_err 5.000s 802.562us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 25 25 100.00
aes_alert_reset 30.000s 102.928us 25 25 100.00
sec_cm_main_config_shadow 18 20 90.00
aes_shadow_reg_errors 26.000s 10026.576us 18 20 90.00
sec_cm_gcm_config_shadow 18 20 90.00
aes_shadow_reg_errors 26.000s 10026.576us 18 20 90.00
sec_cm_main_config_sparse 138 145 95.17
aes_smoke 9.000s 244.525us 10 10 100.00
aes_stress 26.000s 961.342us 10 10 100.00
aes_alert_reset 30.000s 102.928us 25 25 100.00
aes_core_fi 60.000s 10004.007us 93 100 93.00
sec_cm_gcm_config_sparse 153 160 95.62
aes_config_error 32.000s 762.371us 50 50 100.00
aes_stress 26.000s 961.342us 10 10 100.00
aes_core_fi 60.000s 10004.007us 93 100 93.00
sec_cm_aux_config_shadow 18 20 90.00
aes_shadow_reg_errors 26.000s 10026.576us 18 20 90.00
sec_cm_aux_config_regwen 20 20 100.00
aes_readability 3.000s 64.076us 10 10 100.00
aes_stress 26.000s 961.342us 10 10 100.00
sec_cm_key_sideload 20 20 100.00
aes_stress 26.000s 961.342us 10 10 100.00
aes_sideload 38.000s 1261.383us 10 10 100.00
sec_cm_key_sw_unreadable 10 10 100.00
aes_readability 3.000s 64.076us 10 10 100.00
sec_cm_data_reg_sw_unreadable 10 10 100.00
aes_readability 3.000s 64.076us 10 10 100.00
sec_cm_key_sec_wipe 10 10 100.00
aes_readability 3.000s 64.076us 10 10 100.00
sec_cm_iv_config_sec_wipe 10 10 100.00
aes_readability 3.000s 64.076us 10 10 100.00
sec_cm_data_reg_sec_wipe 10 10 100.00
aes_readability 3.000s 64.076us 10 10 100.00
sec_cm_data_reg_key_sca 10 10 100.00
aes_stress 26.000s 961.342us 10 10 100.00
sec_cm_key_masking 10 10 100.00
aes_stress 26.000s 961.342us 10 10 100.00
sec_cm_main_fsm_sparse 10 10 100.00
aes_fi 6.000s 111.129us 10 10 100.00
sec_cm_main_fsm_redun 652 685 95.18
aes_fi 6.000s 111.129us 10 10 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 57.000s 10005.074us 340 350 97.14
aes_ctr_fi 28.000s 106.286us 25 25 100.00
sec_cm_cipher_fsm_sparse 10 10 100.00
aes_fi 6.000s 111.129us 10 10 100.00
sec_cm_cipher_fsm_redun 627 660 95.00
aes_fi 6.000s 111.129us 10 10 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 57.000s 10005.074us 340 350 97.14
sec_cm_cipher_ctr_redun 340 350 97.14
aes_cipher_fi 57.000s 10005.074us 340 350 97.14
sec_cm_ctr_fsm_sparse 10 10 100.00
aes_fi 6.000s 111.129us 10 10 100.00
sec_cm_ctr_fsm_redun 312 335 93.13
aes_fi 6.000s 111.129us 10 10 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_ctr_fi 28.000s 106.286us 25 25 100.00
sec_cm_ghash_fsm_sparse 10 10 100.00
aes_fi 6.000s 111.129us 10 10 100.00
sec_cm_ctrl_sparse 652 685 95.18
aes_fi 6.000s 111.129us 10 10 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 57.000s 10005.074us 340 350 97.14
aes_ctr_fi 28.000s 106.286us 25 25 100.00
sec_cm_main_fsm_global_esc 25 25 100.00
aes_alert_reset 30.000s 102.928us 25 25 100.00
sec_cm_main_fsm_local_esc 652 685 95.18
aes_fi 6.000s 111.129us 10 10 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 57.000s 10005.074us 340 350 97.14
aes_ctr_fi 28.000s 106.286us 25 25 100.00
sec_cm_cipher_fsm_local_esc 652 685 95.18
aes_fi 6.000s 111.129us 10 10 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 57.000s 10005.074us 340 350 97.14
aes_ctr_fi 28.000s 106.286us 25 25 100.00
sec_cm_ctr_fsm_local_esc 312 335 93.13
aes_fi 6.000s 111.129us 10 10 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_ctr_fi 28.000s 106.286us 25 25 100.00
sec_cm_ghash_fsm_local_esc 10 10 100.00
aes_fi 6.000s 111.129us 10 10 100.00
sec_cm_data_reg_local_esc 627 660 95.00
aes_fi 6.000s 111.129us 10 10 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 57.000s 10005.074us 340 350 97.14
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
aes_stress_all_with_rand_reset 109.000s 6811.931us 2 10 20.00

Error Messages

   Test seed line log context
Job timed out after * minutes 13 test runs
aes_control_fi 58823114362187174145141246764915054159774967024870588601292318912235159628160 None
aes_control_fi 16617142948108397781659520627890748458979646795057739632759743632131044533440 None
aes_control_fi 6619981014655377616736782422570824122834713236322269755643490140839327267952 None
aes_control_fi 62372656548860261232680799396962222532022953651271055685326599392844749227918 None
aes_control_fi 93221884901586496944943017978010494915305206174077218434408293691955669722267 None
aes_control_fi 84553236423169087786737409898332753049435548258942854277099125529160354458892 None
aes_control_fi 110733107377541265179454309406830208253323785620145178262147410009930750588090 None
aes_control_fi 89136562421642304938920097652063439320556603668488824855348476266736469962535 None
aes_control_fi 109926880941684946275306001055127444078118377962753403448876005384732987392958 None
aes_control_fi 61929085241620265326539651400814902537722822295126792127992146062936386161159 None
aes_control_fi 77562652102537328763329795353259522954364697564548211003045526389005023961191 None
aes_control_fi 4887630740228092636094643544391169755355226652394529893438890552953001719219 None
aes_control_fi 20810002697985630362168967334713385371560295260711862282240076953291266971219 None
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 10 test runs
aes_control_fi 75307240875932857235042967097013714536824615605833877858853875679815877050180 137
UVM_INFO @ 10019135587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 7225545762890155864121783502523537608453881398536247901180595648295714086527 144
UVM_INFO @ 10017377256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 92779674159987036554483747497790999109340581944177338347453790574691632524634 141
UVM_INFO @ 10003946121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 105976317944242426457126835714536573468573377828178785335139150578402957914490 145
UVM_INFO @ 10017645038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 19394853493262594045170603349086118563541235247766222023072463794499562519363 148
UVM_INFO @ 10006049663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 61096874756622184647987684518490156648144462830103734374198609284564462849425 147
UVM_INFO @ 10073462184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 89550460442034785747238854304199292438498062451059243823326926666098120568072 138
UVM_INFO @ 10015419314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 90790310321154296226078135205935184116881608745697704205490705355703294092431 143
UVM_INFO @ 10012614112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 112779517279580660573753928899562559710166230922175353738070321697171420014006 141
UVM_INFO @ 10016657957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 48041950500975632854063324727550517909728906915190313245755247426057376596253 150
UVM_INFO @ 10025544660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 10 test runs
aes_cipher_fi 62482568476099516617493814250357233440785528571340583576668944750860816447780 146
UVM_INFO @ 10005074485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 17235472314098500746063566590930922607704611739545211970806995035381820333124 138
UVM_INFO @ 10014951036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 50067039040010351036657582512866676750471970661589480085240820024969532457494 150
UVM_INFO @ 10063535868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 90902460979106635472409238103191252282214587572129702835132071975994353769988 143
UVM_INFO @ 10005310639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 28904618343866204878239831806918990880625048137657324598091802158065306482303 139
UVM_INFO @ 10011672340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 104265817041845408788851795006730754880700300275028726722000875042040873811542 140
UVM_INFO @ 10012648258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 103641137366399854063951652924711386738136021912523734612334029889329659615654 147
UVM_INFO @ 10032015709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 91659973837741429832690006542269673937968459135887706298626262453617571931867 143
UVM_INFO @ 10009988297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 67128769794886091190065657077998133330422370606533783000778931932675817098922 146
UVM_INFO @ 10005813009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 81444364458993567443975377136419474603560068730537288369610729491001275602982 146
UVM_INFO @ 10025339863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 7 test runs
aes_core_fi 17022155880696797465284584645906035415821888493968437362880510574020224152325 144
UVM_INFO @ 10018189765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 74609864429616298162968576381007287138461873830713999204269164374747933329318 146
UVM_INFO @ 10028559046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 107165031712293349981874319159225666886798116795965049520088145077534416989699 142
UVM_INFO @ 10127445449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 63163234268308436850913802652370744252681500760177948232826817044796383414248 147
UVM_INFO @ 10003646731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 106747387148030670617133093592251442900499634413964879042880634418501258886798 137
UVM_INFO @ 10013201302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 34547845571075738793645310762495683538342675243743290964844600296367082115488 155
UVM_INFO @ 10004006625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 91419166688253203652475432135218975553403330496391733867326777400595153174347 140
UVM_INFO @ 10011669372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 3 test runs
aes_stress_all_with_rand_reset 75126541063445271679631609105686239632993166654754996114007764647538901395760 570
UVM_INFO @ 919983849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 71120660017550272899546310282186069068716671223344712792339682133907009335199 1269
UVM_INFO @ 2833746445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 40518164990016148750980856749061497150586172516817367342455500797321845828072 658
UVM_INFO @ 1480108893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 89549848236060976420276681277416970106796783648076331266991467742666644255764 338
UVM_INFO @ 462717638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 95024054406663137191441384123489685873724949306700483732380414661560195132918 1635
UVM_INFO @ 1610736603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
aes_stress_all_with_rand_reset 105239992054656527507598998068348327709148507380012190208301371399778611495502 2358
UVM_INFO @ 5061268965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 69542088083728503879996313364513732363805020595458915533948012098072144678405 883
UVM_INFO @ 1677646180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq__shadow_reg_errors.svh:336) [aes_common_vseq] ctrl_shadowed update_err alert timeout 1 test run
aes_shadow_reg_errors 25623479423621787658696399700298396643354494548270594226997713518839311467195 107
UVM_INFO @ 10026575570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 35291563804040119698153575092895492228486139285601127945091329457127062153627 841
UVM_INFO @ 647060944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 1 test run
aes_shadow_reg_errors 23902779172665609227906499426432742780266828726571502655622767428245326950730 106
UVM_INFO @ 52386039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---