Simulation Results: aes/unmasked

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.16 %
  • code
  • 93.28 %
  • assert
  • 97.92 %
  • func
  • 97.29 %
  • block
  • 94.11 %
  • line
  • 95.66 %
  • branch
  • 87.54 %
  • toggle
  • 98.08 %
  • FSM
  • 91.85 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.69%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 96.152us 1 1 100.00
smoke 10 10 100.00
aes_smoke 3.000s 86.438us 10 10 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 114.862us 1 1 100.00
csr_rw 5 5 100.00
aes_csr_rw 3.000s 81.244us 5 5 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 1363.962us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 87.033us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 82.478us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
aes_csr_rw 3.000s 81.244us 5 5 100.00
aes_csr_aliasing 3.000s 87.033us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 70 70 100.00
aes_smoke 3.000s 86.438us 10 10 100.00
aes_config_error 5.000s 138.735us 50 50 100.00
aes_stress 4.000s 110.540us 10 10 100.00
key_length 70 70 100.00
aes_smoke 3.000s 86.438us 10 10 100.00
aes_config_error 5.000s 138.735us 50 50 100.00
aes_stress 4.000s 110.540us 10 10 100.00
back2back 35 35 100.00
aes_stress 4.000s 110.540us 10 10 100.00
aes_b2b 9.000s 112.809us 25 25 100.00
backpressure 10 10 100.00
aes_stress 4.000s 110.540us 10 10 100.00
multi_message 95 95 100.00
aes_smoke 3.000s 86.438us 10 10 100.00
aes_config_error 5.000s 138.735us 50 50 100.00
aes_stress 4.000s 110.540us 10 10 100.00
aes_alert_reset 4.000s 158.564us 25 25 100.00
failure_test 85 85 100.00
aes_man_cfg_err 2.000s 92.486us 10 10 100.00
aes_config_error 5.000s 138.735us 50 50 100.00
aes_alert_reset 4.000s 158.564us 25 25 100.00
trigger_clear_test 10 10 100.00
aes_clear 3.000s 144.087us 10 10 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 117.651us 1 1 100.00
reset_recovery 25 25 100.00
aes_alert_reset 4.000s 158.564us 25 25 100.00
stress 10 10 100.00
aes_stress 4.000s 110.540us 10 10 100.00
sideload 20 20 100.00
aes_stress 4.000s 110.540us 10 10 100.00
aes_sideload 4.000s 162.216us 10 10 100.00
deinitialization 10 10 100.00
aes_deinit 3.000s 81.770us 10 10 100.00
stress_all 10 10 100.00
aes_stress_all 28.000s 728.736us 10 10 100.00
alert_test 10 10 100.00
aes_alert_test 2.000s 66.437us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
aes_tl_errors 4.000s 466.992us 25 25 100.00
tl_d_illegal_access 25 25 100.00
aes_tl_errors 4.000s 466.992us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
aes_csr_hw_reset 1.000s 114.862us 1 1 100.00
aes_csr_rw 3.000s 81.244us 5 5 100.00
aes_csr_aliasing 3.000s 87.033us 1 1 100.00
aes_same_csr_outstanding 3.000s 142.176us 5 5 100.00
tl_d_partial_access 12 12 100.00
aes_csr_hw_reset 1.000s 114.862us 1 1 100.00
aes_csr_rw 3.000s 81.244us 5 5 100.00
aes_csr_aliasing 3.000s 87.033us 1 1 100.00
aes_same_csr_outstanding 3.000s 142.176us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 10 10 100.00
aes_reseed 5.000s 75.989us 10 10 100.00
fault_inject 617 660 93.48
aes_fi 5.000s 124.133us 9 10 90.00
aes_control_fi 61.000s 0.000us 281 300 93.67
aes_cipher_fi 61.000s 0.000us 327 350 93.43
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 247.582us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 247.582us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 247.582us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 247.582us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
aes_shadow_reg_errors_with_csr_rw 4.000s 341.540us 19 20 95.00
tl_intg_err 29 30 96.67
aes_sec_cm 6.000s 549.339us 5 5 100.00
aes_tl_intg_err 30.000s 10103.080us 24 25 96.00
sec_cm_bus_integrity 24 25 96.00
aes_tl_intg_err 30.000s 10103.080us 24 25 96.00
sec_cm_lc_escalate_en_intersig_mubi 25 25 100.00
aes_alert_reset 4.000s 158.564us 25 25 100.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 247.582us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 247.582us 20 20 100.00
sec_cm_main_config_sparse 138 145 95.17
aes_smoke 3.000s 86.438us 10 10 100.00
aes_stress 4.000s 110.540us 10 10 100.00
aes_alert_reset 4.000s 158.564us 25 25 100.00
aes_core_fi 147.000s 10029.101us 93 100 93.00
sec_cm_gcm_config_sparse 153 160 95.62
aes_config_error 5.000s 138.735us 50 50 100.00
aes_stress 4.000s 110.540us 10 10 100.00
aes_core_fi 147.000s 10029.101us 93 100 93.00
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 247.582us 20 20 100.00
sec_cm_aux_config_regwen 20 20 100.00
aes_readability 3.000s 145.486us 10 10 100.00
aes_stress 4.000s 110.540us 10 10 100.00
sec_cm_key_sideload 20 20 100.00
aes_stress 4.000s 110.540us 10 10 100.00
aes_sideload 4.000s 162.216us 10 10 100.00
sec_cm_key_sw_unreadable 10 10 100.00
aes_readability 3.000s 145.486us 10 10 100.00
sec_cm_data_reg_sw_unreadable 10 10 100.00
aes_readability 3.000s 145.486us 10 10 100.00
sec_cm_key_sec_wipe 10 10 100.00
aes_readability 3.000s 145.486us 10 10 100.00
sec_cm_iv_config_sec_wipe 10 10 100.00
aes_readability 3.000s 145.486us 10 10 100.00
sec_cm_data_reg_sec_wipe 10 10 100.00
aes_readability 3.000s 145.486us 10 10 100.00
sec_cm_data_reg_key_sca 10 10 100.00
aes_stress 4.000s 110.540us 10 10 100.00
sec_cm_key_masking 10 10 100.00
aes_stress 4.000s 110.540us 10 10 100.00
sec_cm_main_fsm_sparse 9 10 90.00
aes_fi 5.000s 124.133us 9 10 90.00
sec_cm_main_fsm_redun 642 685 93.72
aes_fi 5.000s 124.133us 9 10 90.00
aes_control_fi 61.000s 0.000us 281 300 93.67
aes_cipher_fi 61.000s 0.000us 327 350 93.43
aes_ctr_fi 2.000s 53.196us 25 25 100.00
sec_cm_cipher_fsm_sparse 9 10 90.00
aes_fi 5.000s 124.133us 9 10 90.00
sec_cm_cipher_fsm_redun 617 660 93.48
aes_fi 5.000s 124.133us 9 10 90.00
aes_control_fi 61.000s 0.000us 281 300 93.67
aes_cipher_fi 61.000s 0.000us 327 350 93.43
sec_cm_cipher_ctr_redun 327 350 93.43
aes_cipher_fi 61.000s 0.000us 327 350 93.43
sec_cm_ctr_fsm_sparse 9 10 90.00
aes_fi 5.000s 124.133us 9 10 90.00
sec_cm_ctr_fsm_redun 315 335 94.03
aes_fi 5.000s 124.133us 9 10 90.00
aes_control_fi 61.000s 0.000us 281 300 93.67
aes_ctr_fi 2.000s 53.196us 25 25 100.00
sec_cm_ghash_fsm_sparse 9 10 90.00
aes_fi 5.000s 124.133us 9 10 90.00
sec_cm_ctrl_sparse 642 685 93.72
aes_fi 5.000s 124.133us 9 10 90.00
aes_control_fi 61.000s 0.000us 281 300 93.67
aes_cipher_fi 61.000s 0.000us 327 350 93.43
aes_ctr_fi 2.000s 53.196us 25 25 100.00
sec_cm_main_fsm_global_esc 25 25 100.00
aes_alert_reset 4.000s 158.564us 25 25 100.00
sec_cm_main_fsm_local_esc 642 685 93.72
aes_fi 5.000s 124.133us 9 10 90.00
aes_control_fi 61.000s 0.000us 281 300 93.67
aes_cipher_fi 61.000s 0.000us 327 350 93.43
aes_ctr_fi 2.000s 53.196us 25 25 100.00
sec_cm_cipher_fsm_local_esc 642 685 93.72
aes_fi 5.000s 124.133us 9 10 90.00
aes_control_fi 61.000s 0.000us 281 300 93.67
aes_cipher_fi 61.000s 0.000us 327 350 93.43
aes_ctr_fi 2.000s 53.196us 25 25 100.00
sec_cm_ctr_fsm_local_esc 315 335 94.03
aes_fi 5.000s 124.133us 9 10 90.00
aes_control_fi 61.000s 0.000us 281 300 93.67
aes_ctr_fi 2.000s 53.196us 25 25 100.00
sec_cm_ghash_fsm_local_esc 9 10 90.00
aes_fi 5.000s 124.133us 9 10 90.00
sec_cm_data_reg_local_esc 617 660 93.48
aes_fi 5.000s 124.133us 9 10 90.00
aes_control_fi 61.000s 0.000us 281 300 93.67
aes_cipher_fi 61.000s 0.000us 327 350 93.43
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
aes_stress_all_with_rand_reset 57.000s 10690.807us 3 10 30.00

Error Messages

   Test seed line log context
Job timed out after * minutes 22 test runs
aes_cipher_fi 75761407971606273362382952394037227717053413841604018570279594170117562831573 None
aes_cipher_fi 107340762271639006207576244700145673600159047177915563073785806205632069114324 None
aes_cipher_fi 78945286378412663018719666246074788014482554355600784388348363289139744127462 None
aes_control_fi 33773717790521264255074306155893748978478659029334801122143520627437069019421 None
aes_control_fi 46735404549760381335217048646634932994958428851517245023313120718787000558116 None
aes_cipher_fi 112105943145131062661296970687142059679922561775275023830347533406206409992425 None
aes_control_fi 32904068746839388387786239413443388009718187488288640193830224167493920570395 None
aes_control_fi 49264757669171796057824089057828935494332592616944330728119188011440679311778 None
aes_cipher_fi 84234913862057222591058828598650268797437528691817247853118317237682907608829 None
aes_control_fi 14269232851159331128143330577010684509579556978488837339022451129733758474011 None
aes_cipher_fi 26371712118500598772622458888342420605695824068759223692783457865154610854521 None
aes_control_fi 75081488565260896970375300595447698675889758528416081355394079982273200693706 None
aes_control_fi 96983408503497746573132548165812164946540336640208723879507780915759943657121 None
aes_cipher_fi 83915833987756966577798839373337835175178480202690173289016795257669628547588 None
aes_cipher_fi 87516031310868990901178977002074813580772013722654529021583506088606701443972 None
aes_cipher_fi 7842120075638720150508984442245650552371401173196188830327784913795735467257 None
aes_cipher_fi 77193930067696813508843219435071610596171985757211730438793872801742770568809 None
aes_control_fi 90562576939807691284586434596498534198912416647253145741626590224487195960341 None
aes_control_fi 57434288018118986468703069206345612972230626649627528221060352788362842371538 None
aes_cipher_fi 70679437952606489665689591313896983497449304903178295217280108956455683277233 None
aes_cipher_fi 16202172775868820622949986728197894524955607689121895673105020450466424221547 None
aes_cipher_fi 103899803082946726701394489602457648128708481655819576016208210855362573907464 None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 10 test runs
aes_cipher_fi 71417988081575786773696656723602078611380865699075622895234615331906874886602 149
UVM_INFO @ 10011366509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 17601338739378967485743310930425646034484961377552056846802813895288577671027 145
UVM_INFO @ 10021245196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 100286330521155975753310122976174736194382325750664201736814504370323157024935 150
UVM_INFO @ 10029869079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 12542699123246944184886204682484956223325517122383007020224490371071161909606 141
UVM_INFO @ 10006560726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 63072211678026121757717417749144573615937682267812118420901210518987177916508 143
UVM_INFO @ 10028873739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 111131138492412852429734225338114349340846402065943353384233040959189483769122 144
UVM_INFO @ 10009554218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 69499773131578145788525860314953483746528061001767790863682862027807090654128 138
UVM_INFO @ 10005097066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 82166198642891521960982439553884298149441152091387647635393609079339879213463 139
UVM_INFO @ 10008167323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 96038462542425728089045929988832692403771589724325662336794720781335116901355 145
UVM_INFO @ 10003503923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 26937884551065225113627158819129898368824926826362756320738197373967007346017 141
UVM_INFO @ 10017960530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 10 test runs
aes_control_fi 57468238007751850312249645606051380549519368776581657056403294770962598833498 143
UVM_INFO @ 10003219160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 33878780955233253048361126051999032738989787226579915247679340806204764422795 141
UVM_INFO @ 10008937082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 39642358290483569784796180874052354781229837204285631317671613367797508968060 139
UVM_INFO @ 10002420469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 34290178106522218818344719269630207642084568660224726952742469849505858931842 149
UVM_INFO @ 10007302424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 97249531118323195205553531786873740589946788257775264151492984379070759927855 142
UVM_INFO @ 10006816683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 84884525443284602034004610730346271985426285561684471568550524515725673001070 141
UVM_INFO @ 10006539113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 54655845196822987315289080098258420858924806003038373829460142539840904472642 137
UVM_INFO @ 10017945070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 105938767781469000999260426227766642611160579764857144706157887917716142020272 144
UVM_INFO @ 10005644336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 57039566310378260305354190721521399957814148478401687280019694678721641028365 143
UVM_INFO @ 10006274529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 45822382747387769790926105540071150234263750469888009136848457503469694115215 144
UVM_INFO @ 10025188134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 4 test runs
aes_core_fi 10089064794239588786114907482925617019861295250676768964335463360659619499086 146
UVM_INFO @ 10057615559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 96748305883811503323444215168856639239640510239262934245869963273330187044565 141
UVM_INFO @ 10044302977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 63371196131716720338903971390851211789797242773675912321734470313668447490448 143
UVM_INFO @ 10008521828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 37966966922432744359416686144997923213090726932626942085313186345365713033531 151
UVM_INFO @ 10009380793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 98218704186527995722970603371322792845784355401654018917252105462244906321736 2360
UVM_INFO @ 845530679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 62445545666736194483482028810802750376064139679395922622139857679446145412173 893
UVM_INFO @ 535373551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 58230018966583338889779438896072458251729822921592935393677955697163031410144 746
UVM_INFO @ 2401955466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 10512129531959039905164270087641423336345108773095840897288769942494099372885 1762
UVM_INFO @ 10690807442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 1 test run
aes_fi 98555480469073157915485424615033638258891033822462948305394167764408184051357 769
UVM_INFO @ 163980144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 5700072380777650367274617045425236218766244519344368577829132735344512049582 165
UVM_INFO @ 52000286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
aes_stress_all_with_rand_reset 42792102867338959958940373434699239966876538505962546973159660661766035276101 267
UVM_INFO @ 2026465928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1136): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) 1 test run
aes_stress_all_with_rand_reset 25951462516486642087173750820601912053805801582825155269377048002335224120814 690
UVM_ERROR @ 2868160664 ps: (aes_core.sv:1136) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_INFO @ 2868160664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_common_vseq] wait timeout occurred! 1 test run
aes_tl_intg_err 10206907477235003392998494240444446670251500602288057403369478751196589902847 131
UVM_INFO @ 10103079980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 1 test run
aes_shadow_reg_errors_with_csr_rw 22186454002052999567944620346951840028533349133016232632591663543434547316418 106
UVM_INFO @ 9455091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) 1 test run
aes_core_fi 84905668142730259874447747974551265423841440881315692603465607588843954901358 140
UVM_INFO @ 10029101069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 78778580544980964755306048646246472519692706330266672301821840079219456301406 139
UVM_INFO @ 10017159292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) 1 test run
aes_core_fi 5204613984447663429323462853296041618620935130565783900034756867878055454383 143
UVM_INFO @ 10039914195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---