Simulation Results: alert_handler

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.65 %
  • code
  • 98.41 %
  • assert
  • 98.88 %
  • func
  • 98.67 %
  • line
  • 99.97 %
  • branch
  • 99.97 %
  • cond
  • 97.40 %
  • toggle
  • 96.33 %
  • FSM
  • 98.39 %
Validation stages
V1
100.00%
V2
92.21%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
alert_handler_smoke 51.290s 5366.892us 10 10 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.540s 57.626us 1 1 100.00
csr_rw 5 5 100.00
alert_handler_csr_rw 10.080s 212.469us 5 5 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 235.550s 3984.750us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 170.880s 2342.697us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
alert_handler_csr_mem_rw_with_rand_reset 10.890s 105.181us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
alert_handler_csr_rw 10.080s 212.469us 5 5 100.00
alert_handler_csr_aliasing 170.880s 2342.697us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 25 25 100.00
alert_handler_esc_alert_accum 284.710s 10462.653us 25 25 100.00
esc_timeout 50 50 100.00
alert_handler_esc_intr_timeout 74.530s 4578.016us 50 50 100.00
entropy 25 25 100.00
alert_handler_entropy 2315.720s 163483.011us 25 25 100.00
sig_int_fail 50 50 100.00
alert_handler_sig_int_fail 66.780s 1248.192us 50 50 100.00
clk_skew 10 10 100.00
alert_handler_smoke 51.290s 5366.892us 10 10 100.00
random_alerts 10 10 100.00
alert_handler_random_alerts 57.360s 3480.275us 10 10 100.00
random_classes 50 50 100.00
alert_handler_random_classes 67.500s 2425.371us 50 50 100.00
ping_timeout 8 25 32.00
alert_handler_ping_timeout 455.290s 13515.571us 8 25 32.00
lpg 80 80 100.00
alert_handler_lpg 2782.010s 233963.034us 50 50 100.00
alert_handler_lpg_stub_clk 2873.720s 54808.545us 30 30 100.00
stress_all 50 50 100.00
alert_handler_stress_all 3942.910s 81820.536us 50 50 100.00
alert_handler_entropy_stress_test 1 20 5.00
alert_handler_entropy_stress 23.210s 2945.399us 1 20 5.00
alert_handler_alert_accum_saturation 20 20 100.00
alert_handler_alert_accum_saturation 4.840s 188.326us 20 20 100.00
intr_test 10 10 100.00
alert_handler_intr_test 2.580s 12.540us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
alert_handler_tl_errors 25.320s 1799.007us 25 25 100.00
tl_d_illegal_access 25 25 100.00
alert_handler_tl_errors 25.320s 1799.007us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
alert_handler_csr_hw_reset 5.540s 57.626us 1 1 100.00
alert_handler_csr_rw 10.080s 212.469us 5 5 100.00
alert_handler_csr_aliasing 170.880s 2342.697us 1 1 100.00
alert_handler_same_csr_outstanding 50.260s 2143.113us 5 5 100.00
tl_d_partial_access 12 12 100.00
alert_handler_csr_hw_reset 5.540s 57.626us 1 1 100.00
alert_handler_csr_rw 10.080s 212.469us 5 5 100.00
alert_handler_csr_aliasing 170.880s 2342.697us 1 1 100.00
alert_handler_same_csr_outstanding 50.260s 2143.113us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
alert_handler_shadow_reg_errors 345.350s 11878.014us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
alert_handler_shadow_reg_errors 345.350s 11878.014us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
alert_handler_shadow_reg_errors 345.350s 11878.014us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
alert_handler_shadow_reg_errors 345.350s 11878.014us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
alert_handler_shadow_reg_errors_with_csr_rw 1105.900s 16673.803us 20 20 100.00
tl_intg_err 30 30 100.00
alert_handler_sec_cm 30.990s 1866.699us 5 5 100.00
alert_handler_tl_intg_err 71.360s 4200.871us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
alert_handler_tl_intg_err 71.360s 4200.871us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
alert_handler_shadow_reg_errors 345.350s 11878.014us 20 20 100.00
sec_cm_ping_timer_config_regwen 10 10 100.00
alert_handler_smoke 51.290s 5366.892us 10 10 100.00
sec_cm_alert_config_regwen 10 10 100.00
alert_handler_smoke 51.290s 5366.892us 10 10 100.00
sec_cm_alert_loc_config_regwen 10 10 100.00
alert_handler_smoke 51.290s 5366.892us 10 10 100.00
sec_cm_class_config_regwen 10 10 100.00
alert_handler_smoke 51.290s 5366.892us 10 10 100.00
sec_cm_alert_intersig_diff 50 50 100.00
alert_handler_sig_int_fail 66.780s 1248.192us 50 50 100.00
sec_cm_lpg_intersig_mubi 50 50 100.00
alert_handler_lpg 2782.010s 233963.034us 50 50 100.00
sec_cm_esc_intersig_diff 50 50 100.00
alert_handler_sig_int_fail 66.780s 1248.192us 50 50 100.00
sec_cm_alert_rx_intersig_bkgn_chk 25 25 100.00
alert_handler_entropy 2315.720s 163483.011us 25 25 100.00
sec_cm_esc_tx_intersig_bkgn_chk 25 25 100.00
alert_handler_entropy 2315.720s 163483.011us 25 25 100.00
sec_cm_esc_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 30.990s 1866.699us 5 5 100.00
sec_cm_ping_timer_fsm_sparse 5 5 100.00
alert_handler_sec_cm 30.990s 1866.699us 5 5 100.00
sec_cm_esc_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 30.990s 1866.699us 5 5 100.00
sec_cm_ping_timer_fsm_local_esc 5 5 100.00
alert_handler_sec_cm 30.990s 1866.699us 5 5 100.00
sec_cm_esc_timer_fsm_global_esc 5 5 100.00
alert_handler_sec_cm 30.990s 1866.699us 5 5 100.00
sec_cm_accu_ctr_redun 5 5 100.00
alert_handler_sec_cm 30.990s 1866.699us 5 5 100.00
sec_cm_esc_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 30.990s 1866.699us 5 5 100.00
sec_cm_ping_timer_ctr_redun 5 5 100.00
alert_handler_sec_cm 30.990s 1866.699us 5 5 100.00
sec_cm_ping_timer_lfsr_redun 5 5 100.00
alert_handler_sec_cm 30.990s 1866.699us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
alert_handler_stress_all_with_rand_reset 455.070s 4653.201us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 19 test runs
alert_handler_entropy_stress 94751959682939937125353776647232447994847610303578630941804737253798029219176 188
UVM_INFO @ 1784817616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 61848765324988686371451691039143050698611375736390155972051029125476998954137 194
UVM_INFO @ 198596543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 96410771924871531592180904497316712834644452254591415904411646306707178402665 152
UVM_INFO @ 553649763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 106442644584822885801337623061320279194229796986632633687610927187375574744398 182
UVM_INFO @ 659537730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 3313447201584733567640702602010013542975722241628688534732150543951156457771 184
UVM_INFO @ 400541440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 12603116149922228903773319265185741762921883368475299813195346389234689852994 160
UVM_INFO @ 132218757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 66589552090994552389101158534096265881132421513679817650302276186162265962669 204
UVM_INFO @ 505411830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 84384003300295410098728820016431760728239080000519877540603523154636339139523 200
UVM_INFO @ 200458609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 29504580107188642550053741124161768993751415211745499123827748121456364332656 142
UVM_INFO @ 280529274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 70028832043285967418540451938640594372107954784640653454375401742513062565845 200
UVM_INFO @ 319432925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 89475034310882416688491443217777810901014111531580558920808978477960340243112 128
UVM_INFO @ 105928500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 58476035847964931532667934111626771959987392654071173473475244562113889463322 174
UVM_INFO @ 382548065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 27813868512448734761233649321265708836642286495217559876416898538893442267381 172
UVM_INFO @ 302684773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 54209066679503527358430687631641279940218235429636952238144648070151089229325 198
UVM_INFO @ 409004108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 104628341031193698701786647910130707991360463663466028746833665333109008889211 146
UVM_INFO @ 378026304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 41327509744950346022635055065552743740813180837533896310870386978722544512175 192
UVM_INFO @ 279992541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 66423237626245596414792418203142822806406889976102962081157040533758649136028 182
UVM_INFO @ 572819908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 47433743572439194387975278900180495911735855785069695123201140052218190143036 190
UVM_INFO @ 89921379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_entropy_stress 83223776145627084608676332596120755331082649939506223521909485004732642921085 194
UVM_INFO @ 2945399431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 11 test runs
alert_handler_ping_timeout 1078991455199489063669402344055067715272757906466151198667641788014580767378 94
UVM_INFO @ 5160674881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 48832626294820233567239728251968213240604148111975954643340021396943355617981 126
UVM_INFO @ 31359769631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 17772232033848008929529227524695313127676004692750021320452826354252131461981 99
UVM_INFO @ 5201983807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 28826573700399633081803218810676031603178537536849404351498215654771332106987 87
UVM_INFO @ 1405996564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 38805993695490558747930094211506569200017473109607794163433498375577403887747 103
UVM_INFO @ 6258044354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 7704892993761656038571543749585053157647259417207101661354949346571216721660 105
UVM_INFO @ 21848591017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 13147558906129711113327647998859177855605927933332528428975551775797527024011 129
UVM_INFO @ 52897442753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 83209022413434979670408588231760449556615125207264756086032856871069741000074 96
UVM_INFO @ 14477334440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 10521571231359826370301285796973948110111383081053673409560327104764256810669 96
UVM_INFO @ 18272656888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 97334369360032701055596894120609115255268998097635520686343396290710083186950 105
UVM_INFO @ 21211323939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 62961557389904435094300860968024353670539297071316434300986889801345138075238 108
UVM_INFO @ 5546270955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. 6 test runs
alert_handler_ping_timeout 39157275164258453555478082888603871269777739979618200266949369120228346811102 80
UVM_INFO @ 529315017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 1635207193025019149268250152520180151695552119126982720212667962413752578286 80
UVM_INFO @ 804784347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 72356403580317740682875711404043065158346230199593048777631980850704311164385 80
UVM_INFO @ 204541812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 19635770389520437135454203226117486315413933680839943633368284865248951391922 80
UVM_INFO @ 219098137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 57269065179079079061738015645601852953133545776768792875146120420959540605976 80
UVM_INFO @ 2769555668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
alert_handler_ping_timeout 55504514382889468528509985777025105173535209849237142726804412930428545520652 80
UVM_INFO @ 208843536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 12853742470964007481071780144883106738341852992424537172614127881018220299361 95
UVM_INFO @ 193738845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
alert_handler_stress_all_with_rand_reset 106624195668913917898306244505645073532777252429150263028515638213951599101364 131
UVM_INFO @ 1063012483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---