Simulation Results: clkmgr

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.92 %
  • code
  • 98.68 %
  • assert
  • 95.76 %
  • func
  • 87.31 %
  • line
  • 99.16 %
  • branch
  • 98.95 %
  • cond
  • 96.10 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
76.55%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.930s 217.436us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.610s 158.370us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.370s 84.665us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.260s 372.605us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 2.020s 123.936us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.930s 463.797us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.370s 84.665us 5 5 100.00
clkmgr_csr_aliasing 2.020s 123.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.260s 35.942us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.500s 133.068us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.970s 252.427us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.150s 39.575us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.930s 217.436us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 14.460s 1398.968us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 13.030s 1460.234us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 14.460s 1398.968us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 56.340s 7248.256us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.340s 68.119us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 6.380s 1205.062us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 6.380s 1205.062us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 1.610s 158.370us 1 1 100.00
clkmgr_csr_rw 1.370s 84.665us 5 5 100.00
clkmgr_csr_aliasing 2.020s 123.936us 1 1 100.00
clkmgr_same_csr_outstanding 1.780s 59.956us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 1.610s 158.370us 1 1 100.00
clkmgr_csr_rw 1.370s 84.665us 5 5 100.00
clkmgr_csr_aliasing 2.020s 123.936us 1 1 100.00
clkmgr_same_csr_outstanding 1.780s 59.956us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 14 30 46.67
clkmgr_sec_cm 68.340s 10076.942us 0 5 0.00
clkmgr_tl_intg_err 55.940s 10057.122us 14 25 56.00
shadow_reg_update_error 11 20 55.00
clkmgr_shadow_reg_errors 968.040s 200000.000us 11 20 55.00
shadow_reg_read_clear_staged_value 11 20 55.00
clkmgr_shadow_reg_errors 968.040s 200000.000us 11 20 55.00
shadow_reg_storage_error 11 20 55.00
clkmgr_shadow_reg_errors 968.040s 200000.000us 11 20 55.00
shadowed_reset_glitch 11 20 55.00
clkmgr_shadow_reg_errors 968.040s 200000.000us 11 20 55.00
shadow_reg_update_error_with_csr_rw 12 20 60.00
clkmgr_shadow_reg_errors_with_csr_rw 983.580s 200000.000us 12 20 60.00
sec_cm_bus_integrity 14 25 56.00
clkmgr_tl_intg_err 55.940s 10057.122us 14 25 56.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 14.460s 1398.968us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 13.030s 1460.234us 10 10 100.00
sec_cm_meas_config_shadow 11 20 55.00
clkmgr_shadow_reg_errors 968.040s 200000.000us 11 20 55.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 3.120s 521.432us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 1.520s 57.691us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.620s 139.747us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 9 10 90.00
clkmgr_clk_handshake_intersig_mubi 1.490s 92.610us 9 10 90.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 2.040s 233.165us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.370s 84.665us 5 5 100.00
sec_cm_idle_ctr_redun 0 5 0.00
clkmgr_sec_cm 68.340s 10076.942us 0 5 0.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.370s 84.665us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.370s 84.665us 5 5 100.00
prim_count_check 0 5 0.00
clkmgr_sec_cm 68.340s 10076.942us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 7.110s 834.287us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 139.920s 39115.168us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1030) [clkmgr_common_vseq] timeout wait for alert handshake:fatal_fault 14 test runs
clkmgr_sec_cm 58670719536303310170383845261614625041940662485478678141845958985508255580598 127
UVM_INFO @ 10076942301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 69223157452700480230490258879133781061495041202210067198901592453748183095844 94
UVM_INFO @ 10014191640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 56430430846314669826880668053244097804550111100188509416551853656300858063819 109
UVM_INFO @ 10025764530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 64951515373396735557823546421496581128055502733914244594764888138564994146626 120
UVM_INFO @ 10098255159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 14041393081688655057539348151153583393318857955160822065426213170395619662103 151
UVM_INFO @ 10100673872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 21739046249557665277479354762141643165512957445296158306633536823453325076992 80
UVM_INFO @ 10018965277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 6219924685470505811090894407861179562459849328241932358813039420101781349112 135
UVM_INFO @ 10078479139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 12999402774197278435742931866902232366360625685917260646999096808639033653884 177
UVM_INFO @ 10057122366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 92539092855786440906464601360095042076074702291233332406491986152159026100384 98
UVM_INFO @ 10021766420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 63439074902173591716048194458420329906024047588502658263398422734861699289749 111
UVM_INFO @ 10020012577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 88365219296391308153343941679895311983613499298810398781626061955280901929062 82
UVM_INFO @ 10008539407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 24609251207543470011308799010110325158465588835647742486198664406404500150080 136
UVM_INFO @ 10220355696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 41803584604648471166019658137316586567021328628361023225755498959594767782472 110
UVM_INFO @ 10074868430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 61072987004998465541577709127819746293281868231088965413250071346906885506822 89
UVM_INFO @ 10011542197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 11 test runs
clkmgr_shadow_reg_errors 23576746074063324510395928291544429002503153942362840909566195165584857797775 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 112782952019422977736877396878973983079683690402975926529333603993508287148664 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 29970616174537692565728358286611039738580870604557021353940296717635945288696 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 89443605313626263818666798966795645230844804458855996373903245727846190107369 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 93639375306232347193227273334588056663680275230145640467043554988452860897151 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 24911148639112878948119154097571227553140279040503374006853692641524488598916 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 106728533036931885692230030962152551509702987571737704943715949533005194430233 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 107474778904458362328718535569519170628863581843661560375577632213523411444428 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 46332324783893791206684464357316738385828370241419778830657431035954532390053 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 30496542900230316789528575589236007155562399570787108775995113103928203955964 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 25148366585566354516044146228218882530491154309226274877662343078560611687979 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire 2 test runs
clkmgr_sec_cm 104222179951368137576543457901551530362263484328893960985205634542083255490031 81
UVM_INFO @ 8882386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 23151033746768445644452620775870970663788875052264911822097145430036936361093 139
UVM_INFO @ 72654595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Check_csr_read_clear_staged_val task: check storage_err status 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 99817430500790304625301624798405811664432131262134022568428203743516003966191 75
UVM_INFO @ 81990318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_hints_status (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 32148044595821851523819647612756764786794119026382153618972835148862772009116 75
UVM_INFO @ 2121657724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_ctrl_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 107929450043713657935253923425631923946018677290795863023189964424704051037248 75
UVM_INFO @ 2253516922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Write_and_check_update_error task: check storage_err status 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 58152962847552025987422868207752183869550398155808892632092565664824354867677 75
UVM_INFO @ 29263641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch 1 test run
clkmgr_clk_handshake_intersig_mubi 64074941464198387760934037572507012476278815669650597910084678214470967818258 74
UVM_INFO @ 4473193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 23748042734683503355733426288211776298588552900384053811588041305346026156207 75
UVM_INFO @ 2063494417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 63803394919155434001889022742310757273570697665566960889530945356778255323411 75
UVM_INFO @ 41613424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---