Simulation Results: csrng

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.20 %
  • code
  • 96.26 %
  • assert
  • 95.85 %
  • func
  • 90.50 %
  • block
  • 98.62 %
  • line
  • 99.61 %
  • branch
  • 96.55 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.39%
V2S
99.92%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 20.000s 14.438us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 33.000s 17.168us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 33.000s 21.506us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 36.000s 59.268us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 34.000s 40.616us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 34.000s 73.380us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 33.000s 21.506us 5 5 100.00
csrng_csr_aliasing 34.000s 40.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 35.000s 85.634us 200 200 100.00
alerts 500 500 100.00
csrng_alert 45.000s 268.683us 500 500 100.00
err 500 500 100.00
csrng_err 33.000s 40.348us 500 500 100.00
cmds 4 25 16.00
csrng_cmds 191.000s 15147.126us 4 25 16.00
life cycle 4 25 16.00
csrng_cmds 191.000s 15147.126us 4 25 16.00
stress_all 25 25 100.00
csrng_stress_all 1327.000s 112412.322us 25 25 100.00
intr_test 10 10 100.00
csrng_intr_test 33.000s 45.420us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 34.000s 34.331us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 23.000s 413.958us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 23.000s 413.958us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 33.000s 17.168us 1 1 100.00
csrng_csr_rw 33.000s 21.506us 5 5 100.00
csrng_csr_aliasing 34.000s 40.616us 1 1 100.00
csrng_same_csr_outstanding 23.000s 16.742us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 33.000s 17.168us 1 1 100.00
csrng_csr_rw 33.000s 21.506us 5 5 100.00
csrng_csr_aliasing 34.000s 40.616us 1 1 100.00
csrng_same_csr_outstanding 23.000s 16.742us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 29 30 96.67
csrng_sec_cm 24.000s 48.120us 5 5 100.00
csrng_tl_intg_err 15.000s 82.766us 24 25 96.00
sec_cm_config_regwen 30 30 100.00
csrng_regwen 24.000s 48.159us 25 25 100.00
csrng_csr_rw 33.000s 21.506us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 45.000s 268.683us 500 500 100.00
sec_cm_intersig_mubi 25 25 100.00
csrng_stress_all 1327.000s 112412.322us 25 25 100.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 35.000s 85.634us 200 200 100.00
csrng_err 33.000s 40.348us 500 500 100.00
csrng_sec_cm 24.000s 48.120us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 35.000s 85.634us 200 200 100.00
csrng_err 33.000s 40.348us 500 500 100.00
csrng_sec_cm 24.000s 48.120us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 35.000s 85.634us 200 200 100.00
csrng_err 33.000s 40.348us 500 500 100.00
csrng_sec_cm 24.000s 48.120us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 35.000s 85.634us 200 200 100.00
csrng_err 33.000s 40.348us 500 500 100.00
csrng_sec_cm 24.000s 48.120us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 35.000s 85.634us 200 200 100.00
csrng_err 33.000s 40.348us 500 500 100.00
csrng_sec_cm 24.000s 48.120us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 45.000s 268.683us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 35.000s 85.634us 200 200 100.00
csrng_err 33.000s 40.348us 500 500 100.00
sec_cm_constants_lc_gated 25 25 100.00
csrng_stress_all 1327.000s 112412.322us 25 25 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 45.000s 268.683us 500 500 100.00
sec_cm_tile_link_bus_integrity 24 25 96.00
csrng_tl_intg_err 15.000s 82.766us 24 25 96.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 35.000s 85.634us 200 200 100.00
csrng_err 33.000s 40.348us 500 500 100.00
csrng_sec_cm 24.000s 48.120us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 35.000s 85.634us 200 200 100.00
csrng_err 33.000s 40.348us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 35.000s 85.634us 200 200 100.00
csrng_err 33.000s 40.348us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 35.000s 85.634us 200 200 100.00
csrng_err 33.000s 40.348us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 35.000s 85.634us 200 200 100.00
csrng_err 33.000s 40.348us 500 500 100.00
csrng_sec_cm 24.000s 48.120us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 35.000s 85.634us 200 200 100.00
csrng_err 33.000s 40.348us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 19 test runs
csrng_cmds 42845822747741055573931795767761754324968707159420195746274875141867467036167 130
UVM_INFO @ 400253673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 38768050340354644115116599036175141399318797682506512142966867729831275734217 130
UVM_INFO @ 136399175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 34290408693055854895394534163153235184794308115955859589990412445781021340656 130
UVM_INFO @ 542282353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 74228117572414105939404006724570908960023194151851117807243543345553534532500 130
UVM_INFO @ 75220308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 109654245526586447100601327357967311774770593994450487233313300047728450429592 139
UVM_INFO @ 24336425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 68062807165802717666359277994124465736952710320506085425905731056390329799138 130
UVM_INFO @ 30864083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 109125778983665916728323836030521366294369513806958669609343861212403361461645 140
UVM_INFO @ 144566301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 44938464347489912846427327176934517257197360020656460986513498318434450288307 130
UVM_INFO @ 24819232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 96894479433373648884861865310186614374010846456730229958309948027987784901198 130
UVM_INFO @ 127698008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 2999958493084985692752474627587324683018750246041991664229446539456366076321 130
UVM_INFO @ 35665064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 73575995203202910631589242331987072457474329390964672303726174781960992229632 130
UVM_INFO @ 28288706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 86284236787962915230424649729980533664263015686071961956613929875362694903426 130
UVM_INFO @ 313567195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 66041419236681539544450008681768127021555983916103918028891379636394603934326 140
UVM_INFO @ 208602472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 7753890447635724041468863576423499911179335514804296097948351021435733199342 140
UVM_INFO @ 848491181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 13363654490418670085564356890807680741231030632209873073004495690874758014802 130
UVM_INFO @ 162451762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 14614469413371970137962977703123679684399542000113810599434272381733532000389 130
UVM_INFO @ 561833421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 4910240000851488961740990259379303856880570370091406454612734736644545195571 130
UVM_INFO @ 49653975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 108268001664095466420045039332782799003893224429575593908404091864639212867183 130
UVM_INFO @ 7133849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 34013479122188938146281677842023441721204342369064427539453822223470347337784 130
UVM_INFO @ 66983138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 10 test runs
csrng_stress_all_with_rand_reset 44996290410483216900221252842589913641623615197294327246495721517919607645839 None
csrng_stress_all_with_rand_reset 104703646461291915821011130004653144186098122218267277897920687994738340405150 None
csrng_stress_all_with_rand_reset 101315898623939239585376643772460064344851094755264179371650463335373202701317 None
csrng_stress_all_with_rand_reset 46061395150687845642067498173293448393408913954769457123786021482598712518447 None
csrng_stress_all_with_rand_reset 95350351514792399125550333437944033382183612277547455558477801146037753623065 None
csrng_stress_all_with_rand_reset 57982336186224069055052442098036700108850713686048703344981821032122627175649 None
csrng_stress_all_with_rand_reset 32321278674250744696252309367693120622729599757079098096188871232907037643434 None
csrng_stress_all_with_rand_reset 109229309907545939896573353233900775271336961022860669803101078934228286708353 None
csrng_stress_all_with_rand_reset 73856688638940746842976843515819973263668985972422513545512567520669319819045 None
csrng_stress_all_with_rand_reset 31072453311119595114217341597211513105415988230464071302897479145828763230403 None
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 2 test runs
csrng_cmds 75406800329305559094804530741901236457792891020249062756605223449663874043330 139
UVM_INFO @ 418909775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 49672010091353031403639841792764615719192752529587721760723745835928074240563 139
UVM_INFO @ 43702414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [csrng_common_vseq] expect alert:fatal_alert to fire 1 test run
csrng_tl_intg_err 39216760806636740998745769505608007213041980583027418678697039238632317986805 112
UVM_INFO @ 21707457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---