Simulation Results: edn/edn0

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.33 %
  • code
  • 95.71 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.14 %
  • toggle
  • 97.07 %
  • FSM
  • 91.94 %
Validation stages
V1
100.00%
V2
99.34%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.180s 36.820us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.920s 84.507us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.270s 14.441us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.190s 179.842us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.290s 18.481us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.520s 318.949us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.270s 14.441us 5 5 100.00
edn_csr_aliasing 1.290s 18.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 4.560s 534.729us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 4.560s 534.729us 100 100 100.00
genbits 100 100 100.00
edn_genbits 4.560s 534.729us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.180s 20.291us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.660s 93.854us 200 200 100.00
errs 100 100 100.00
edn_err 1.530s 38.308us 100 100 100.00
disable 96 100 96.00
edn_disable 1.180s 16.704us 50 50 100.00
edn_disable_auto_req_mode 2.320s 500.000us 46 50 92.00
stress_all 30 30 100.00
edn_stress_all 7.550s 340.269us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.100s 18.321us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.240s 81.446us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.520s 236.654us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.520s 236.654us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 0.920s 84.507us 1 1 100.00
edn_csr_rw 1.270s 14.441us 5 5 100.00
edn_csr_aliasing 1.290s 18.481us 1 1 100.00
edn_same_csr_outstanding 1.400s 274.054us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 0.920s 84.507us 1 1 100.00
edn_csr_rw 1.270s 14.441us 5 5 100.00
edn_csr_aliasing 1.290s 18.481us 1 1 100.00
edn_same_csr_outstanding 1.400s 274.054us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 7.960s 1500.242us 5 5 100.00
edn_tl_intg_err 2.730s 130.426us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.290s 41.539us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.660s 93.854us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.960s 1500.242us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.960s 1500.242us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.960s 1500.242us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.960s 1500.242us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.660s 93.854us 200 200 100.00
edn_sec_cm 7.960s 1500.242us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.660s 93.854us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 2.730s 130.426us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 30 90.00
edn_stress_all_with_rand_reset 142.520s 11313.427us 27 30 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
edn_disable_auto_req_mode 96149327931532461074175524388481351840180479621007814892885306904604550869432 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 16216135984984967364628748339164844599451211767076204836519022760567417296161 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 49749742265449184010219576560950418680872351894957291740295624884223981288095 88
UVM_INFO @ 21575601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 98574850355210818896761907331241702964035695618295548807650510071748089018184 88
UVM_INFO @ 14954882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 103059408026723423229729886166012720260938166902476096220216603430716827189652 178
UVM_INFO @ 11313426716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 16594046181448635400741910402177262277588009837555576153887897273751115927922 180
UVM_INFO @ 169423094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_stress_all_with_rand_reset 46375668651332749030911313777737908017109481631835460901681850500653054776084 207
/nightly/current_run/scratch/reseed_opt/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1271284773 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup