Simulation Results

Simulation Results: edn/edn1

24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
95.15 %

code
95.86 %

assert
97.14 %

func
92.44 %

line
98.48 %

branch
94.59 %

cond
94.62 %

toggle
96.15 %

FSM
95.45 %

Validation stages

V1		100.00%
V2		98.85%
V2S		100.00%
V3		80.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	edn_smoke	1.110s	17.665us	10	10	100.00
csr_hw_reset				1	1	100.00
	edn_csr_hw_reset	1.010s	19.341us	1	1	100.00
csr_rw				5	5	100.00
	edn_csr_rw	1.220s	27.133us	5	5	100.00
csr_bit_bash				1	1	100.00
	edn_csr_bit_bash	4.210s	554.976us	1	1	100.00
csr_aliasing				1	1	100.00
	edn_csr_aliasing	1.140s	92.920us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	edn_csr_mem_rw_with_rand_reset	1.460s	54.501us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	edn_csr_rw	1.220s	27.133us	5	5	100.00
	edn_csr_aliasing	1.140s	92.920us	1	1	100.00

600/607 passed

98.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
firmware				100	100	100.00
	edn_genbits	4.770s	624.664us	100	100	100.00
csrng_commands				100	100	100.00
	edn_genbits	4.770s	624.664us	100	100	100.00
genbits				100	100	100.00
	edn_genbits	4.770s	624.664us	100	100	100.00
interrupts				20	20	100.00
	edn_intr	1.310s	48.613us	20	20	100.00
alerts				200	200	100.00
	edn_alert	1.590s	100.059us	200	200	100.00
errs				100	100	100.00
	edn_err	1.610s	26.328us	100	100	100.00
disable				93	100	93.00
	edn_disable	1.270s	14.226us	50	50	100.00
	edn_disable_auto_req_mode	16.010s	500.000us	43	50	86.00
stress_all				30	30	100.00
	edn_stress_all	7.850s	457.874us	30	30	100.00
intr_test				10	10	100.00
	edn_intr_test	0.990s	23.341us	10	10	100.00
alert_test				10	10	100.00
	edn_alert_test	1.010s	52.660us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	edn_tl_errors	3.270s	690.054us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	edn_tl_errors	3.270s	690.054us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	edn_csr_hw_reset	1.010s	19.341us	1	1	100.00
	edn_csr_rw	1.220s	27.133us	5	5	100.00
	edn_csr_aliasing	1.140s	92.920us	1	1	100.00
	edn_same_csr_outstanding	1.430s	465.266us	5	5	100.00
tl_d_partial_access				12	12	100.00
	edn_csr_hw_reset	1.010s	19.341us	1	1	100.00
	edn_csr_rw	1.220s	27.133us	5	5	100.00
	edn_csr_aliasing	1.140s	92.920us	1	1	100.00
	edn_same_csr_outstanding	1.430s	465.266us	5	5	100.00

V2S

235/235 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	edn_sec_cm	4.550s	938.714us	5	5	100.00
	edn_tl_intg_err	9.960s	1196.376us	25	25	100.00
sec_cm_config_regwen				5	5	100.00
	edn_regwen	1.100s	19.261us	5	5	100.00
sec_cm_config_mubi				200	200	100.00
	edn_alert	1.590s	100.059us	200	200	100.00
sec_cm_main_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	4.550s	938.714us	5	5	100.00
sec_cm_ack_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	4.550s	938.714us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	edn_sec_cm	4.550s	938.714us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	edn_sec_cm	4.550s	938.714us	5	5	100.00
sec_cm_main_sm_ctr_local_esc				205	205	100.00
	edn_alert	1.590s	100.059us	200	200	100.00
	edn_sec_cm	4.550s	938.714us	5	5	100.00
sec_cm_cs_rdata_bus_consistency				200	200	100.00
	edn_alert	1.590s	100.059us	200	200	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	edn_tl_intg_err	9.960s	1196.376us	25	25	100.00

24/30 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				24	30	80.00
	edn_stress_all_with_rand_reset	100.380s	31612.246us	24	30	80.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				7 test runs
	edn_disable_auto_req_mode	73941170765600720443550989028877876309055861411129869690993678470027884287913	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	98481245088185762693058205851455456405097502963231721983753313389766541721297	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	30034264166394930056049877817145459520925205185086048126719789570156606703595	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	95575486063286309905464393351657131693398450863892708983996862731647440590381	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	55191435525760779735572434167170374893845652296091212219915699230621008285732	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	94535047971859363621195770670012691711901324637049012656658802966291629971250	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	60181901434982924503152023469140872194838794555290003973029785196198387864853	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				5 test runs
	edn_stress_all_with_rand_reset	93239189737188713019846446668429710291435720926528083884795093133436790495478	128	UVM_INFO @ 180727860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	51761821904302846521019184016667773429501825396505836264953042475813916332232	201	UVM_INFO @ 1317876274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	73974251338614899678210240408052804295090975553696798074248282119901181742959	164	UVM_INFO @ 1723760354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	56268681378956447567511002598309532914203747533406599865802280967263930140357	170	UVM_INFO @ 1889853235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	59376566059692273079758356836210150398518602965587637867734573919406672151861	156	UVM_INFO @ 1841470564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.				1 test run
	edn_stress_all_with_rand_reset	91409228894037170500585344230952973401688662347444313283751903122108291397312	266	UVM_INFO @ 1095928082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---