Simulation Results

Simulation Results: flash_ctrl

24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
97.02 %

code
95.80 %

assert
96.84 %

func
98.42 %

line
96.11 %

branch
97.45 %

cond
94.93 %

toggle
98.66 %

FSM
91.84 %

Validation stages

V1		100.00%
V2		98.72%
V2S		99.37%
V3		100.00%
unmapped		100.00%

70/70 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	147.660s	43.726us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	21.090s	19.015us	5	5	100.00
csr_hw_reset				1	1	100.00
	flash_ctrl_csr_hw_reset	14.480s	34.005us	1	1	100.00
csr_rw				5	5	100.00
	flash_ctrl_csr_rw	16.090s	61.045us	5	5	100.00
csr_bit_bash				1	1	100.00
	flash_ctrl_csr_bit_bash	52.710s	1271.886us	1	1	100.00
csr_aliasing				1	1	100.00
	flash_ctrl_csr_aliasing	22.540s	237.457us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	14.470s	118.389us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	flash_ctrl_csr_rw	16.090s	61.045us	5	5	100.00
	flash_ctrl_csr_aliasing	22.540s	237.457us	1	1	100.00
mem_walk				1	1	100.00
	flash_ctrl_mem_walk	11.320s	16.084us	1	1	100.00
mem_partial_access				1	1	100.00
	flash_ctrl_mem_partial_access	6.840s	31.537us	1	1	100.00

923/935 passed

98.72 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	20.510s	272.045us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	61.290s	92.227us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1630.100s	138700.064us	3	3	100.00
	flash_ctrl_hw_rma_reset	1417.860s	760537.605us	20	20	100.00
	flash_ctrl_lcmgr_intg	13.920s	80.930us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	2363.520s	268539.468us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	301.560s	8190.627us	5	5	100.00
program_reset				30	30	100.00
	flash_ctrl_prog_reset	170.860s	4730.092us	30	30	100.00
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	3986.020s	325758.565us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	91.020s	82.378us	5	5	100.00
rd_buff_eviction_w_ecc				101	105	96.19
	flash_ctrl_rw_evict	33.080s	47.734us	37	40	92.50
	flash_ctrl_rw_evict_all_en	32.640s	42.831us	39	40	97.50
	flash_ctrl_re_evict	33.540s	118.510us	25	25	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	190.040s	27136.152us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	190.040s	27136.152us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	916.490s	63624.389us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	25.300s	1056.274us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	664.280s	3129.796us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	705.260s	6183.051us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	559.400s	429.587us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1611.260s	9673.927us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	13.890s	230.737us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	240.410s	9634.596us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	21.700s	21.837us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	17.090s	52.489us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	887.150s	296.134us	5	5	100.00
secret_partition				129	130	99.23
	flash_ctrl_hw_sec_otp	223.840s	99271.814us	50	50	100.00
	flash_ctrl_otp_reset	115.280s	76.909us	79	80	98.75
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1630.100s	138700.064us	3	3	100.00
interrupts				96	100	96.00
	flash_ctrl_intr_rd	202.480s	7735.316us	38	40	95.00
	flash_ctrl_intr_wr	3604.013s	0.000us	9	10	90.00
	flash_ctrl_intr_rd_slow_flash	413.370s	48968.944us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	3604.011s	0.000us	9	10	90.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	81.410s	1747.576us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	71.070s	890.438us	5	5	100.00
double_bit_err				35	35	100.00
	flash_ctrl_read_word_sweep_derr	18.450s	81.076us	5	5	100.00
	flash_ctrl_ro_derr	123.280s	1338.975us	10	10	100.00
	flash_ctrl_rw_derr	210.090s	7347.391us	10	10	100.00
	flash_ctrl_derr_detect	141.900s	1866.868us	5	5	100.00
	flash_ctrl_integrity	520.220s	4842.502us	5	5	100.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	19.080s	26.360us	5	5	100.00
	flash_ctrl_ro_serr	111.040s	692.911us	10	10	100.00
	flash_ctrl_rw_serr	210.840s	7668.912us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	68.000s	718.880us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	63.120s	14017.749us	5	5	100.00
scramble				60	62	96.77
	flash_ctrl_wo	3604.010s	0.000us	19	20	95.00
	flash_ctrl_write_word_sweep	9.590s	78.076us	1	1	100.00
	flash_ctrl_read_word_sweep	8.070s	36.710us	1	1	100.00
	flash_ctrl_ro	109.170s	1085.582us	20	20	100.00
	flash_ctrl_rw	3603.537s	0.000us	19	20	95.00
filesystem_support				4	5	80.00
	flash_ctrl_fs_sup	2857.550s	200000.000us	4	5	80.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	890.960s	71748.392us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	255.100s	10019.344us	20	20	100.00
alert_test				10	10	100.00
	flash_ctrl_alert_test	12.750s	26.598us	10	10	100.00
intr_test				10	10	100.00
	flash_ctrl_intr_test	13.290s	21.918us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	flash_ctrl_tl_errors	19.250s	484.474us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	flash_ctrl_tl_errors	19.250s	484.474us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	flash_ctrl_csr_hw_reset	14.480s	34.005us	1	1	100.00
	flash_ctrl_csr_rw	16.090s	61.045us	5	5	100.00
	flash_ctrl_csr_aliasing	22.540s	237.457us	1	1	100.00
	flash_ctrl_same_csr_outstanding	13.500s	160.673us	5	5	100.00
tl_d_partial_access				12	12	100.00
	flash_ctrl_csr_hw_reset	14.480s	34.005us	1	1	100.00
	flash_ctrl_csr_rw	16.090s	61.045us	5	5	100.00
	flash_ctrl_csr_aliasing	22.540s	237.457us	1	1	100.00
	flash_ctrl_same_csr_outstanding	13.500s	160.673us	5	5	100.00

V2S

472/475 passed

99.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.570s	221.208us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.570s	221.208us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.570s	221.208us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.570s	221.208us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	93.780s	326.173us	20	20	100.00
tl_intg_err				30	30	100.00
	flash_ctrl_sec_cm	2308.320s	7423.295us	5	5	100.00
	flash_ctrl_tl_intg_err	603.600s	1836.857us	25	25	100.00
sec_cm_reg_bus_integrity				25	25	100.00
	flash_ctrl_tl_intg_err	603.600s	1836.857us	25	25	100.00
sec_cm_host_bus_integrity				25	25	100.00
	flash_ctrl_tl_intg_err	603.600s	1836.857us	25	25	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	26.510s	817.832us	3	3	100.00
	flash_ctrl_wr_intg	11.670s	169.179us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	147.660s	43.726us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				259	260	99.62
	flash_ctrl_otp_reset	115.280s	76.909us	79	80	98.75
	flash_ctrl_disable	21.700s	21.837us	50	50	100.00
	flash_ctrl_sec_info_access	85.750s	1002.082us	50	50	100.00
	flash_ctrl_connect	17.090s	52.489us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	13.950s	41.811us	5	5	100.00
sec_cm_data_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	16.090s	61.045us	5	5	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.570s	221.208us	20	20	100.00
sec_cm_info_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	16.090s	61.045us	5	5	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.570s	221.208us	20	20	100.00
sec_cm_bank_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	16.090s	61.045us	5	5	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.570s	221.208us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	21.700s	21.837us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	26.510s	817.832us	3	3	100.00
	flash_ctrl_access_after_disable	11.480s	19.735us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	20.290s	39.378us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	21.700s	21.837us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	25.300s	1056.274us	10	10	100.00
sec_cm_mem_scramble				19	20	95.00
	flash_ctrl_rw	3603.537s	0.000us	19	20	95.00
sec_cm_mem_integrity				25	25	100.00
	flash_ctrl_rw_serr	210.840s	7668.912us	10	10	100.00
	flash_ctrl_rw_derr	210.090s	7347.391us	10	10	100.00
	flash_ctrl_integrity	520.220s	4842.502us	5	5	100.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1630.100s	138700.064us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2308.320s	7423.295us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2308.320s	7423.295us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2308.320s	7423.295us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2308.320s	7423.295us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	20.210s	831.042us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				4	5	80.00
	flash_ctrl_phy_host_grant_err	12.550s	39.632us	4	5	80.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	13.880s	79.331us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2308.320s	7423.295us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2308.320s	7423.295us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2308.320s	7423.295us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	28.070s	73.750us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	476.050s	830.488us	3	3	100.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				4 test runs
	flash_ctrl_intr_wr	112000567530676224462893557798045663992642819169809899062972326680596355437992	None
	flash_ctrl_intr_wr_slow_flash	69942173074643608653053328095553133949301040121499681978135635630779593887273	None
	flash_ctrl_wo	101325303860131753810125808591867576931494004666900616500094320913783339538312	None
	flash_ctrl_rw	91726065494774699437293924411216548355511705849728067906240738910702969834067	None
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:				2 test runs
	flash_ctrl_rw_evict	53789903095019460529821062249570756791199562589910821986329009804116090834660	108	UVM_INFO @ 11030.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict_all_en	61143987150965237973509143317794764505978474563728270996392430431587188905977	108	UVM_INFO @ 45573.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value:				2 test runs
	flash_ctrl_rw_evict	90821508917350470211019015560502879289733918809051601924474330570532223676990	108	UVM_INFO @ 49958.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	52782576722667708930882316563329356975427741216054989352035223632110027606555	108	UVM_INFO @ 17674.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'				1 test run
	flash_ctrl_phy_host_grant_err	4391603509841943002794058534738244891923999130438969171896123628631077301847	125	UVM_ERROR @ 90535.6 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 90535.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue				1 test run
	flash_ctrl_fs_sup	47217127116466872852395236066351844242213593613348327246733193716082021463234	108	UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp aefd67_f58ea4ae:ffffffff_ffffffff mismatch!!				1 test run
	flash_ctrl_intr_rd	101754868245033789085284603851068765268813561830924417895090825958611292199529	108	UVM_INFO @ 2728406.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp a512d1a_*:ffffffff_ffffffff mismatch!!				1 test run
	flash_ctrl_intr_rd	35431864038342546613896908224400148650719041979351889345063793094038947585258	108	UVM_INFO @ 3081880.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'dst_req_o'				1 test run
	flash_ctrl_otp_reset	108067885327057912633292464118206764474912699301831359265076078892608720920590	213	UVM_ERROR @ 93907.5 ns: (prim_sync_reqack.sv:355) [ASSERT FAILED] SyncReqAckAckNeedsReq UVM_INFO @ 93907.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---