Simulation Results: hmac

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.87 %
  • code
  • 99.25 %
  • assert
  • 97.36 %
  • func
  • 100.00 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.85 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 18.630s 1614.746us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.040s 42.459us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.330s 38.351us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.520s 1416.456us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.000s 4217.283us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 857.110s 73487.453us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.330s 38.351us 5 5 100.00
hmac_csr_aliasing 5.000s 4217.283us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 66.100s 4373.969us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 96.520s 2511.128us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 235.230s 25807.159us 30 30 100.00
hmac_test_sha384_vectors 510.140s 47161.247us 75 75 100.00
hmac_test_sha512_vectors 519.860s 60313.044us 75 75 100.00
hmac_test_hmac256_vectors 14.350s 2360.488us 50 50 100.00
hmac_test_hmac384_vectors 15.610s 1289.485us 60 60 100.00
hmac_test_hmac512_vectors 18.060s 1002.592us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 49.400s 9615.103us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 908.320s 25012.210us 10 10 100.00
error 10 10 100.00
hmac_error 131.940s 91533.172us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 106.570s 41474.877us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 18.630s 1614.746us 10 10 100.00
hmac_long_msg 66.100s 4373.969us 10 10 100.00
hmac_back_pressure 96.520s 2511.128us 25 25 100.00
hmac_datapath_stress 908.320s 25012.210us 10 10 100.00
hmac_burst_wr 49.400s 9615.103us 50 50 100.00
hmac_stress_all 2094.410s 217518.197us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 18.630s 1614.746us 10 10 100.00
hmac_long_msg 66.100s 4373.969us 10 10 100.00
hmac_back_pressure 96.520s 2511.128us 25 25 100.00
hmac_datapath_stress 908.320s 25012.210us 10 10 100.00
hmac_wipe_secret 106.570s 41474.877us 10 10 100.00
hmac_test_sha256_vectors 235.230s 25807.159us 30 30 100.00
hmac_test_sha384_vectors 510.140s 47161.247us 75 75 100.00
hmac_test_sha512_vectors 519.860s 60313.044us 75 75 100.00
hmac_test_hmac256_vectors 14.350s 2360.488us 50 50 100.00
hmac_test_hmac384_vectors 15.610s 1289.485us 60 60 100.00
hmac_test_hmac512_vectors 18.060s 1002.592us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 18.630s 1614.746us 10 10 100.00
hmac_long_msg 66.100s 4373.969us 10 10 100.00
hmac_back_pressure 96.520s 2511.128us 25 25 100.00
hmac_datapath_stress 908.320s 25012.210us 10 10 100.00
hmac_burst_wr 49.400s 9615.103us 50 50 100.00
hmac_error 131.940s 91533.172us 10 10 100.00
hmac_wipe_secret 106.570s 41474.877us 10 10 100.00
hmac_test_sha256_vectors 235.230s 25807.159us 30 30 100.00
hmac_test_sha384_vectors 510.140s 47161.247us 75 75 100.00
hmac_test_sha512_vectors 519.860s 60313.044us 75 75 100.00
hmac_test_hmac256_vectors 14.350s 2360.488us 50 50 100.00
hmac_test_hmac384_vectors 15.610s 1289.485us 60 60 100.00
hmac_test_hmac512_vectors 18.060s 1002.592us 75 75 100.00
hmac_stress_all 2094.410s 217518.197us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2094.410s 217518.197us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.970s 96.298us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.980s 18.533us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 5.280s 263.834us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 5.280s 263.834us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.040s 42.459us 1 1 100.00
hmac_csr_rw 1.330s 38.351us 5 5 100.00
hmac_csr_aliasing 5.000s 4217.283us 1 1 100.00
hmac_same_csr_outstanding 2.710s 134.362us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.040s 42.459us 1 1 100.00
hmac_csr_rw 1.330s 38.351us 5 5 100.00
hmac_csr_aliasing 5.000s 4217.283us 1 1 100.00
hmac_same_csr_outstanding 2.710s 134.362us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.570s 1049.657us 5 5 100.00
hmac_tl_intg_err 5.120s 1057.522us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.120s 1057.522us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 18.630s 1614.746us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.410s 131.055us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 573.330s 65685.860us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.910s 244.598us 1 1 100.00