Simulation Results: keymgr

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.78 %
  • code
  • 98.49 %
  • assert
  • 97.72 %
  • func
  • 91.13 %
  • line
  • 99.16 %
  • branch
  • 98.90 %
  • cond
  • 98.00 %
  • toggle
  • 98.72 %
  • FSM
  • 97.67 %
Validation stages
V1
100.00%
V2
98.83%
V2S
99.38%
V3
65.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 30 30 100.00
keymgr_smoke 16.710s 1231.635us 30 30 100.00
random 30 30 100.00
keymgr_random 31.250s 1615.109us 30 30 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.390s 76.104us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.800s 25.304us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 25.710s 4641.539us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 5.290s 366.120us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 2.170s 452.281us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.800s 25.304us 5 5 100.00
keymgr_csr_aliasing 5.290s 366.120us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 89.570s 7903.444us 50 50 100.00
sideload 80 80 100.00
keymgr_sideload 19.760s 1413.322us 20 20 100.00
keymgr_sideload_kmac 35.580s 1748.299us 20 20 100.00
keymgr_sideload_aes 19.790s 914.829us 20 20 100.00
keymgr_sideload_otbn 28.440s 1871.147us 20 20 100.00
direct_to_disabled_state 30 30 100.00
keymgr_direct_to_disabled 24.690s 1341.943us 30 30 100.00
lc_disable 49 50 98.00
keymgr_lc_disable 10.360s 556.026us 49 50 98.00
kmac_error_response 19 20 95.00
keymgr_kmac_rsp_err 11.400s 1541.707us 19 20 95.00
invalid_sw_input 20 20 100.00
keymgr_sw_invalid_input 32.070s 4112.037us 20 20 100.00
invalid_hw_input 49 50 98.00
keymgr_hwsw_invalid_input 45.620s 14742.212us 49 50 98.00
sync_async_fault_cross 20 20 100.00
keymgr_sync_async_fault_cross 11.220s 392.937us 20 20 100.00
stress_all 48 50 96.00
keymgr_stress_all 496.080s 59158.790us 48 50 96.00
intr_test 10 10 100.00
keymgr_intr_test 1.130s 11.145us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.360s 14.192us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 4.730s 116.200us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 4.730s 116.200us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.390s 76.104us 1 1 100.00
keymgr_csr_rw 1.800s 25.304us 5 5 100.00
keymgr_csr_aliasing 5.290s 366.120us 1 1 100.00
keymgr_same_csr_outstanding 4.980s 112.967us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.390s 76.104us 1 1 100.00
keymgr_csr_rw 1.800s 25.304us 5 5 100.00
keymgr_csr_aliasing 5.290s 366.120us 1 1 100.00
keymgr_same_csr_outstanding 4.980s 112.967us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 18.150s 669.056us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 18.150s 669.056us 5 5 100.00
keymgr_tl_intg_err 11.690s 4311.045us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 6.220s 278.077us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 6.220s 278.077us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 6.220s 278.077us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 6.220s 278.077us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 12.950s 425.212us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 18.150s 669.056us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 18.150s 669.056us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 11.690s 4311.045us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 6.220s 278.077us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 89.570s 7903.444us 50 50 100.00
sec_cm_reseed_config_regwen 35 35 100.00
keymgr_random 31.250s 1615.109us 30 30 100.00
keymgr_csr_rw 1.800s 25.304us 5 5 100.00
sec_cm_sw_binding_config_regwen 35 35 100.00
keymgr_random 31.250s 1615.109us 30 30 100.00
keymgr_csr_rw 1.800s 25.304us 5 5 100.00
sec_cm_max_key_ver_config_regwen 35 35 100.00
keymgr_random 31.250s 1615.109us 30 30 100.00
keymgr_csr_rw 1.800s 25.304us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 49 50 98.00
keymgr_lc_disable 10.360s 556.026us 49 50 98.00
sec_cm_constants_consistency 49 50 98.00
keymgr_hwsw_invalid_input 45.620s 14742.212us 49 50 98.00
sec_cm_intersig_consistency 49 50 98.00
keymgr_hwsw_invalid_input 45.620s 14742.212us 49 50 98.00
sec_cm_hw_key_sw_noaccess 30 30 100.00
keymgr_random 31.250s 1615.109us 30 30 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 17.160s 3240.596us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.150s 669.056us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.150s 669.056us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 18.150s 669.056us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 11.820s 415.009us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 49 50 98.00
keymgr_lc_disable 10.360s 556.026us 49 50 98.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 18.150s 669.056us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.150s 669.056us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 18.150s 669.056us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 11.820s 415.009us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 11.820s 415.009us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 18.150s 669.056us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 11.820s 415.009us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.150s 669.056us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 11.820s 415.009us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 13 20 65.00
keymgr_stress_all_with_rand_reset 27.060s 4547.345us 13 20 65.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
keymgr_stress_all_with_rand_reset 11441186261857428514668095003259944484730229561965659028373210065448019436243 146
UVM_INFO @ 237637332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 37026501657990880384016139890099090910948470162375624948373840527561019956920 143
UVM_INFO @ 452833727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 40236140631126008455147916288807883741982885017363316588445618864211204959154 345
UVM_INFO @ 248304496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 18145485898574683643096893980899534269094558327112615612757761200914116409661 193
UVM_INFO @ 629020704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 51264341981943858059223621886471532531806659885572687862258166487932202992372 279
UVM_INFO @ 277656303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 11137090119060974279982810377792957233331957167106048046428891090686499047022 145
UVM_INFO @ 105944222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 3 test runs
keymgr_stress_all 7239199079990356334645979498179898571774580947670215323153222497170299386705 838
UVM_INFO @ 453324573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 115115071719391344349084810457894047667934931720334515795403127926188450434326 698
UVM_INFO @ 265524418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_hwsw_invalid_input 2949025282581950207152424408173615945314188606980898588286159073575136991957 510
UVM_INFO @ 139854151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) 1 test run
keymgr_stress_all_with_rand_reset 28520376203207795925722727418411809537271101209097582000947829777048627164052 490
UVM_INFO @ 1022109042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly 1 test run
keymgr_kmac_rsp_err 67591972065763925667729584377556045199008352773017405692134029751617661415599 222
UVM_INFO @ 9118068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_* 1 test run
keymgr_lc_disable 13728703918867396622427694638425918633929651770309055455593750621221253813010 99
UVM_INFO @ 55436640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---