Simulation Results: kmac/masked

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.79 %
  • code
  • 94.39 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 80.99 %
Validation stages
V1
100.00%
V2
99.76%
V2S
99.41%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 88.080s 9362.028us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.510s 138.801us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.510s 70.477us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 10.230s 8133.676us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 4.740s 1058.455us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 2.760s 118.782us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.510s 70.477us 5 5 100.00
kmac_csr_aliasing 4.740s 1058.455us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.920s 35.933us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.370s 124.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 4269.590s 126735.025us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 1392.870s 36712.592us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1819.700s 18527.277us 5 5 100.00
kmac_test_vectors_sha3_256 2826.720s 89272.795us 5 5 100.00
kmac_test_vectors_sha3_384 1308.720s 13852.043us 5 5 100.00
kmac_test_vectors_sha3_512 1234.940s 33473.920us 5 5 100.00
kmac_test_vectors_shake_128 2026.840s 21417.601us 5 5 100.00
kmac_test_vectors_shake_256 2698.710s 178167.089us 5 5 100.00
kmac_test_vectors_kmac 3.650s 105.165us 5 5 100.00
kmac_test_vectors_kmac_xof 3.950s 114.240us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 440.570s 23774.281us 20 20 100.00
app 25 25 100.00
kmac_app 377.580s 111540.318us 25 25 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 338.950s 15325.411us 10 10 100.00
entropy_refresh 20 20 100.00
kmac_entropy_refresh 387.120s 27011.741us 20 20 100.00
error 20 20 100.00
kmac_error 420.400s 39922.932us 20 20 100.00
key_error 20 20 100.00
kmac_key_error 16.660s 12497.534us 20 20 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.800s 140.028us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 44.820s 2609.251us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 34.660s 1785.187us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 83.210s 31063.023us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 29.590s 1039.542us 50 50 100.00
stress_all 19 20 95.00
kmac_stress_all 2755.320s 55888.428us 19 20 95.00
intr_test 10 10 100.00
kmac_intr_test 1.230s 147.119us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.300s 29.264us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
kmac_tl_errors 4.600s 133.376us 25 25 100.00
tl_d_illegal_access 25 25 100.00
kmac_tl_errors 4.600s 133.376us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 1.510s 138.801us 1 1 100.00
kmac_csr_rw 1.510s 70.477us 5 5 100.00
kmac_csr_aliasing 4.740s 1058.455us 1 1 100.00
kmac_same_csr_outstanding 3.310s 98.292us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 1.510s 138.801us 1 1 100.00
kmac_csr_rw 1.510s 70.477us 5 5 100.00
kmac_csr_aliasing 4.740s 1058.455us 1 1 100.00
kmac_same_csr_outstanding 3.310s 98.292us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.630s 846.102us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.630s 846.102us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.630s 846.102us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.630s 846.102us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 6.060s 495.852us 19 20 95.00
tl_intg_err 30 30 100.00
kmac_sec_cm 101.970s 25546.856us 5 5 100.00
kmac_tl_intg_err 6.480s 355.762us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
kmac_tl_intg_err 6.480s 355.762us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 29.590s 1039.542us 50 50 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 88.080s 9362.028us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 440.570s 23774.281us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.630s 846.102us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 101.970s 25546.856us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 101.970s 25546.856us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 101.970s 25546.856us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 88.080s 9362.028us 20 20 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 29.590s 1039.542us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 101.970s 25546.856us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 470.700s 179254.324us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 88.080s 9362.028us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
kmac_stress_all_with_rand_reset 145.490s 20343.841us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * 1 test run
kmac_shadow_reg_errors_with_csr_rw 60344064428586081457118686303576618093047800494180298791386296072588743757210 262
UVM_INFO @ 38253462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * 1 test run
kmac_stress_all 84988184362360440973518662533327226696248667555500805934784190345445099379626 331
UVM_INFO @ 41692552276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---