Simulation Results: kmac/unmasked

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.45 %
  • code
  • 92.19 %
  • assert
  • 97.90 %
  • func
  • 96.25 %
  • line
  • 97.56 %
  • branch
  • 95.85 %
  • cond
  • 94.83 %
  • toggle
  • 100.00 %
  • FSM
  • 72.73 %
Validation stages
V1
100.00%
V2
95.02%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 53.570s 5405.838us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.250s 16.653us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.710s 329.752us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 24.670s 5994.183us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 4.710s 76.043us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 3.230s 332.216us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.710s 329.752us 5 5 100.00
kmac_csr_aliasing 4.710s 76.043us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 1.100s 22.488us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.500s 63.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 4649.390s 896447.733us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 878.370s 36826.671us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2456.810s 187564.062us 5 5 100.00
kmac_test_vectors_sha3_256 1987.940s 58494.399us 5 5 100.00
kmac_test_vectors_sha3_384 1289.560s 45179.904us 5 5 100.00
kmac_test_vectors_sha3_512 882.890s 32757.523us 5 5 100.00
kmac_test_vectors_shake_128 2839.890s 886285.040us 5 5 100.00
kmac_test_vectors_shake_256 301.160s 11098.250us 5 5 100.00
kmac_test_vectors_kmac 3.270s 215.614us 5 5 100.00
kmac_test_vectors_kmac_xof 2.920s 140.489us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 332.700s 52545.780us 20 20 100.00
app 25 25 100.00
kmac_app 237.630s 22073.284us 25 25 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 286.730s 112862.509us 10 10 100.00
entropy_refresh 20 20 100.00
kmac_entropy_refresh 285.160s 18338.911us 20 20 100.00
error 20 20 100.00
kmac_error 394.870s 21537.151us 20 20 100.00
key_error 20 20 100.00
kmac_key_error 9.730s 3792.158us 20 20 100.00
sideload_invalid 29 50 58.00
kmac_sideload_invalid 121.610s 10033.926us 29 50 58.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 32.260s 1729.475us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 39.480s 6287.210us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 57.290s 23783.246us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 31.810s 905.177us 50 50 100.00
stress_all 20 20 100.00
kmac_stress_all 2400.010s 265176.021us 20 20 100.00
intr_test 10 10 100.00
kmac_intr_test 1.160s 15.914us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.190s 180.599us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
kmac_tl_errors 5.350s 195.770us 25 25 100.00
tl_d_illegal_access 25 25 100.00
kmac_tl_errors 5.350s 195.770us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 1.250s 16.653us 1 1 100.00
kmac_csr_rw 1.710s 329.752us 5 5 100.00
kmac_csr_aliasing 4.710s 76.043us 1 1 100.00
kmac_same_csr_outstanding 3.210s 236.402us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 1.250s 16.653us 1 1 100.00
kmac_csr_rw 1.710s 329.752us 5 5 100.00
kmac_csr_aliasing 4.710s 76.043us 1 1 100.00
kmac_same_csr_outstanding 3.210s 236.402us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.580s 97.547us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.580s 97.547us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.580s 97.547us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.580s 97.547us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.700s 942.775us 20 20 100.00
tl_intg_err 30 30 100.00
kmac_sec_cm 57.260s 31616.049us 5 5 100.00
kmac_tl_intg_err 6.570s 1615.091us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
kmac_tl_intg_err 6.570s 1615.091us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 31.810s 905.177us 50 50 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 53.570s 5405.838us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 332.700s 52545.780us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.580s 97.547us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 57.260s 31616.049us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 57.260s 31616.049us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 57.260s 31616.049us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 53.570s 5405.838us 20 20 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 31.810s 905.177us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 57.260s 31616.049us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 264.880s 8855.057us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 53.570s 5405.838us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
kmac_stress_all_with_rand_reset 212.620s 4141.155us 6 10 60.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) 4 test runs
kmac_sideload_invalid 34029091421112077455815446460031574435579453628748347990794103474472473303163 79
UVM_INFO @ 10021484879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 7802372862549035547711958435070098395458474831229516696207414646053012350205 79
UVM_INFO @ 10022748059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 72694293337477709863509762826458149004314706186380816048099753165862277469155 79
UVM_INFO @ 10022489755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 38006342870317533607282429058105374449535303742885897685301613722066529519170 79
UVM_INFO @ 10021279661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) 3 test runs
kmac_sideload_invalid 5567429592982761114753295782998568136704717740951373150215134931874807614193 80
UVM_INFO @ 10033926136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 68372555240209349060422252081983638602062655874660340159706266724200013081495 80
UVM_INFO @ 10045664528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 40871430496646443520678923271520561989512478809626995880810185456512087073987 81
UVM_INFO @ 10390174256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 3 test runs
kmac_sideload_invalid 66499822801044401070948895468886293850992012678371054620467208808151285643658 78
UVM_INFO @ 10017771958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 44932721522549535746548286992553277738433198084312906953665833039498226295654 78
UVM_INFO @ 10034110126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 37045329796505296933345302573588590404831676634441385081094412501002457476589 78
UVM_INFO @ 10127674628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 2 test runs
kmac_stress_all_with_rand_reset 90570158787983336574850409527534097778814637844960521901420960329219029919119 435
UVM_INFO @ 4141155081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 55468646643046277767213251625599933392446196148025627331874701458785852387685 342
UVM_INFO @ 3400062071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
kmac_stress_all_with_rand_reset 30947444682469097026934154030601809233368110464021557659276144578392795579993 356
UVM_INFO @ 4514036287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 53524957443019404993394584444416129008562835029053201854256792956639513602537 206
UVM_INFO @ 8040633208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) 2 test runs
kmac_sideload_invalid 19822210808870385003344270830802466696660981526634997606051840422072624604360 81
UVM_INFO @ 10177633298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 73473336443642769820558304375231247100872875130364983784946163663793694773582 82
UVM_INFO @ 10100568371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 2 test runs
kmac_sideload_invalid 46177501171403619250713738055515878537370088641813593107696125669413499928394 86
UVM_INFO @ 10132886264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 98747493454460057476796437476727632515767026785048449967109477203426567625079 87
UVM_INFO @ 10071607687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) 1 test run
kmac_sideload_invalid 28736211168089592024996495994839149120206448008560944594890302892099501794520 100
UVM_INFO @ 10208721282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) 1 test run
kmac_sideload_invalid 104641409570205679564209619726194382115156226298583285981843604786063679934957 103
UVM_INFO @ 10179391173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) 1 test run
kmac_sideload_invalid 56253938761496381166197292871604083549320776652009011750495628318070236376769 106
UVM_INFO @ 10614669428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=29) 1 test run
kmac_sideload_invalid 75612538664578942005306968152009072887494506708794766545022787593560729447697 112
UVM_INFO @ 10394993949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) 1 test run
kmac_sideload_invalid 89590556967650507406422836657568153095301863444775810023336703158852839118244 83
UVM_INFO @ 10047989629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) 1 test run
kmac_sideload_invalid 40166816217961955189763036785007832161763165561972715007616005929439511909766 89
UVM_INFO @ 12018053575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) 1 test run
kmac_sideload_invalid 27386733495072831685287468148958427786188047323511408572419863714739263162935 104
UVM_INFO @ 12517546863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---