Simulation Results: lc_ctrl/volatile_unlock_disabled

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.01 %
  • code
  • 86.00 %
  • assert
  • 94.13 %
  • func
  • 95.91 %
  • line
  • 97.28 %
  • branch
  • 94.14 %
  • cond
  • 81.77 %
  • toggle
  • 89.54 %
  • FSM
  • 67.29 %
Validation stages
V1
100.00%
V2
99.54%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 6.230s 879.415us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.460s 15.878us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.540s 36.507us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.280s 37.653us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.730s 114.547us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.950s 29.240us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.540s 36.507us 5 5 100.00
lc_ctrl_csr_aliasing 1.730s 114.547us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 30 30 100.00
lc_ctrl_state_post_trans 9.280s 410.237us 30 30 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 15.910s 347.402us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.360s 23.312us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.210s 241.066us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 14.100s 420.369us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 14.320s 960.267us 19 20 95.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 14.100s 420.369us 20 20 100.00
lc_ctrl_prog_failure 4.210s 241.066us 20 20 100.00
lc_ctrl_errors 14.320s 960.267us 19 20 95.00
lc_ctrl_security_escalation 11.210s 3968.358us 20 20 100.00
lc_ctrl_jtag_state_failure 69.010s 3073.576us 20 20 100.00
lc_ctrl_jtag_prog_failure 12.930s 780.162us 20 20 100.00
lc_ctrl_jtag_errors 63.040s 6203.130us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 13.250s 618.003us 20 20 100.00
lc_ctrl_jtag_state_post_trans 24.140s 897.593us 20 20 100.00
lc_ctrl_jtag_prog_failure 12.930s 780.162us 20 20 100.00
lc_ctrl_jtag_errors 63.040s 6203.130us 19 20 95.00
lc_ctrl_jtag_access 15.510s 2556.768us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 25.540s 2121.656us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.480s 370.498us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.890s 333.611us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 23.510s 9622.370us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 12.110s 1337.125us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.850s 104.281us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.460s 277.730us 10 10 100.00
lc_ctrl_jtag_alert_test 5.080s 158.128us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 13.630s 8328.487us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.500s 15.313us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 392.430s 76094.327us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.620s 81.428us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.810s 113.435us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.810s 113.435us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.460s 15.878us 1 1 100.00
lc_ctrl_csr_rw 1.540s 36.507us 5 5 100.00
lc_ctrl_csr_aliasing 1.730s 114.547us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.090s 40.733us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.460s 15.878us 1 1 100.00
lc_ctrl_csr_rw 1.540s 36.507us 5 5 100.00
lc_ctrl_csr_aliasing 1.730s 114.547us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.090s 40.733us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 11.360s 554.801us 5 5 100.00
lc_ctrl_tl_intg_err 5.060s 1049.962us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 5.060s 1049.962us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 15.910s 347.402us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 14.100s 420.369us 20 20 100.00
lc_ctrl_sec_cm 11.360s 554.801us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 14.100s 420.369us 20 20 100.00
lc_ctrl_sec_cm 11.360s 554.801us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.100s 420.369us 20 20 100.00
lc_ctrl_sec_cm 11.360s 554.801us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.100s 420.369us 20 20 100.00
lc_ctrl_sec_cm 11.360s 554.801us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 14.100s 420.369us 20 20 100.00
lc_ctrl_sec_cm 11.360s 554.801us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.100s 420.369us 20 20 100.00
lc_ctrl_sec_cm 11.360s 554.801us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.100s 420.369us 20 20 100.00
lc_ctrl_sec_cm 11.360s 554.801us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 14.100s 420.369us 20 20 100.00
lc_ctrl_sec_cm 11.360s 554.801us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 11.210s 3968.358us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 50 50 100.00
lc_ctrl_state_post_trans 9.280s 410.237us 30 30 100.00
lc_ctrl_jtag_state_post_trans 24.140s 897.593us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 19.990s 804.053us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 19.990s 804.053us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 11.950s 456.935us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.250s 578.466us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.250s 578.466us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 120.520s 55532.412us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 92474945420258721947024624603788859352247530845444190040887715534730248626989 8110
UVM_INFO @ 13183872699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 102425584643646536961652684034393286899870939073905568912544035509164290681495 151
UVM_INFO @ 1162293568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 17870051622151284552072702879154215854388664620729029144604071977827111111276 207
UVM_INFO @ 167033569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64797106309713061176175776659858186449173412081869124332539394191867186286285 642
UVM_INFO @ 6669900855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 101237293524018364758072709356747684084795542234327605092755855352874736920526 3242
UVM_INFO @ 2840234563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_errors 53017439491272175442378018151758450517703238182346352654431715258601534682838 1550
UVM_INFO @ 402533906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 3374073972220462394694272850986227043084479028736240742125562793528939827368 1621
UVM_INFO @ 509002963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---