Simulation Results: lc_ctrl/volatile_unlock_enabled

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.27 %
  • code
  • 86.06 %
  • assert
  • 94.13 %
  • func
  • 96.62 %
  • line
  • 97.26 %
  • branch
  • 94.09 %
  • cond
  • 82.11 %
  • toggle
  • 89.54 %
  • FSM
  • 67.29 %
Validation stages
V1
100.00%
V2
98.40%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 6.280s 336.582us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.500s 16.980us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.410s 52.869us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.010s 147.809us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.630s 226.937us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.610s 19.699us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.410s 52.869us 5 5 100.00
lc_ctrl_csr_aliasing 1.630s 226.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 30 30 100.00
lc_ctrl_state_post_trans 7.640s 1087.150us 30 30 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 17.380s 700.261us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.380s 12.532us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.440s 139.921us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 14.090s 3777.572us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 14.260s 3136.898us 19 20 95.00
security_escalation 133 140 95.00
lc_ctrl_state_failure 14.090s 3777.572us 20 20 100.00
lc_ctrl_prog_failure 3.440s 139.921us 20 20 100.00
lc_ctrl_errors 14.260s 3136.898us 19 20 95.00
lc_ctrl_security_escalation 9.520s 391.724us 20 20 100.00
lc_ctrl_jtag_state_failure 79.310s 17785.637us 20 20 100.00
lc_ctrl_jtag_prog_failure 23.230s 2335.147us 20 20 100.00
lc_ctrl_jtag_errors 70.310s 3552.974us 14 20 70.00
jtag_access 204 210 97.14
lc_ctrl_jtag_smoke 14.490s 686.791us 20 20 100.00
lc_ctrl_jtag_state_post_trans 24.130s 4884.548us 20 20 100.00
lc_ctrl_jtag_prog_failure 23.230s 2335.147us 20 20 100.00
lc_ctrl_jtag_errors 70.310s 3552.974us 14 20 70.00
lc_ctrl_jtag_access 21.970s 4725.141us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 30.200s 5471.512us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.380s 469.965us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.470s 729.461us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 39.570s 4992.330us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 10.880s 2588.923us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.720s 172.024us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 6.270s 228.168us 10 10 100.00
lc_ctrl_jtag_alert_test 1.880s 501.444us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 13.170s 653.396us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.630s 54.509us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 345.520s 45771.479us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.710s 27.059us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.730s 649.524us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.730s 649.524us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.500s 16.980us 1 1 100.00
lc_ctrl_csr_rw 1.410s 52.869us 5 5 100.00
lc_ctrl_csr_aliasing 1.630s 226.937us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.550s 94.327us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.500s 16.980us 1 1 100.00
lc_ctrl_csr_rw 1.410s 52.869us 5 5 100.00
lc_ctrl_csr_aliasing 1.630s 226.937us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.550s 94.327us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 8.150s 529.531us 5 5 100.00
lc_ctrl_tl_intg_err 5.000s 144.856us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 5.000s 144.856us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 17.380s 700.261us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 14.090s 3777.572us 20 20 100.00
lc_ctrl_sec_cm 8.150s 529.531us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 14.090s 3777.572us 20 20 100.00
lc_ctrl_sec_cm 8.150s 529.531us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.090s 3777.572us 20 20 100.00
lc_ctrl_sec_cm 8.150s 529.531us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.090s 3777.572us 20 20 100.00
lc_ctrl_sec_cm 8.150s 529.531us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 14.090s 3777.572us 20 20 100.00
lc_ctrl_sec_cm 8.150s 529.531us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.090s 3777.572us 20 20 100.00
lc_ctrl_sec_cm 8.150s 529.531us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.090s 3777.572us 20 20 100.00
lc_ctrl_sec_cm 8.150s 529.531us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 14.090s 3777.572us 20 20 100.00
lc_ctrl_sec_cm 8.150s 529.531us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 9.520s 391.724us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 50 50 100.00
lc_ctrl_state_post_trans 7.640s 1087.150us 30 30 100.00
lc_ctrl_jtag_state_post_trans 24.130s 4884.548us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 13.650s 591.205us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 13.650s 591.205us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 16.500s 2092.765us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 13.920s 11054.185us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 13.920s 11054.185us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 117.960s 24220.138us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 7 test runs
lc_ctrl_jtag_errors 70511480234689270643730897767192792925601684990941605146297675701027406967261 1622
UVM_INFO @ 1772182149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 63878193143550600816352757636438089282849942772376535175655306242801156269292 1384
UVM_INFO @ 2360700556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 68912714673926783729465332424722552887374279948980935805279948455208865012568 2720
UVM_INFO @ 174465977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 53389398653847167724267838884657860633949746176039561131872335451592715654958 2998
UVM_INFO @ 4450591031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 108947308494291156843832690201344436557717877682681636923715040999824603140933 979
UVM_INFO @ 1888712072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 54357718005858931942503873739598759423603623074831552957973366304511735951587 194
UVM_INFO @ 72731339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 70178989864571231678433393332598846033642940979296279818722229334358808344243 426
UVM_INFO @ 115698611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 39569090322358829253156211054097976423649013555553214388887961034932711330 206
UVM_INFO @ 1060927395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43595463509886129451054090251355786192433340975788015306922818644159097711681 14781
UVM_INFO @ 11276355957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47256189274487264750791223831995778121318955124023639802112797003211524030212 5254
UVM_INFO @ 4838907620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 1206359641924158578962923687362827190251819577987055637998800906856976463424 505
UVM_INFO @ 12012464821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 82297516556488856262356100527370206697558805045712471417535427429955800279821 7709
UVM_INFO @ 1855459461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---