Simulation Results

Simulation Results: otp_ctrl

24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
91.16 %

code
85.99 %

assert
94.75 %

func
92.74 %

line
90.33 %

branch
86.80 %

cond
94.10 %

toggle
95.68 %

FSM
63.02 %

Validation stages

V1		92.31%
V2		96.21%
V2S		95.76%
V3		25.74%

24/26 passed

92.31 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	otp_ctrl_wake_up	1.630s	191.190us	1	1	100.00
smoke				10	10	100.00
	otp_ctrl_smoke	9.840s	624.617us	10	10	100.00
csr_hw_reset				1	1	100.00
	otp_ctrl_csr_hw_reset	2.240s	137.065us	1	1	100.00
csr_rw				5	5	100.00
	otp_ctrl_csr_rw	2.260s	149.493us	5	5	100.00
csr_bit_bash				1	1	100.00
	otp_ctrl_csr_bit_bash	4.150s	1277.371us	1	1	100.00
csr_aliasing				1	1	100.00
	otp_ctrl_csr_aliasing	3.560s	163.064us	1	1	100.00
csr_mem_rw_with_rand_reset				3	5	60.00
	otp_ctrl_csr_mem_rw_with_rand_reset	3.400s	974.409us	3	5	60.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otp_ctrl_csr_rw	2.260s	149.493us	5	5	100.00
	otp_ctrl_csr_aliasing	3.560s	163.064us	1	1	100.00
mem_walk				1	1	100.00
	otp_ctrl_mem_walk	1.960s	545.971us	1	1	100.00
mem_partial_access				1	1	100.00
	otp_ctrl_mem_partial_access	1.340s	130.076us	1	1	100.00

710/738 passed

96.21 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
dai_access_partition_walk				1	1	100.00
	otp_ctrl_partition_walk	17.270s	2460.026us	1	1	100.00
init_fail				300	300	100.00
	otp_ctrl_init_fail	7.720s	2619.830us	300	300	100.00
partition_check				38	60	63.33
	otp_ctrl_background_chks	25.770s	16948.744us	10	10	100.00
	otp_ctrl_check_fail	30.170s	13161.057us	28	50	56.00
regwen_during_otp_init				30	30	100.00
	otp_ctrl_regwen	12.340s	5163.796us	30	30	100.00
partition_lock				30	30	100.00
	otp_ctrl_dai_lock	58.210s	7295.285us	30	30	100.00
interface_key_check				10	10	100.00
	otp_ctrl_parallel_key_req	56.340s	26827.029us	10	10	100.00
lc_interactions				210	210	100.00
	otp_ctrl_parallel_lc_req	18.720s	781.152us	10	10	100.00
	otp_ctrl_parallel_lc_esc	26.410s	1799.010us	200	200	100.00
otp_dai_errors				10	10	100.00
	otp_ctrl_dai_errs	34.940s	19639.518us	10	10	100.00
otp_macro_errors				5	10	50.00
	otp_ctrl_macro_errs	25.360s	2771.930us	5	10	50.00
test_access				10	10	100.00
	otp_ctrl_test_access	29.080s	3773.523us	10	10	100.00
stress_all				9	10	90.00
	otp_ctrl_stress_all	264.020s	43800.510us	9	10	90.00
intr_test				10	10	100.00
	otp_ctrl_intr_test	1.930s	611.070us	10	10	100.00
alert_test				10	10	100.00
	otp_ctrl_alert_test	2.860s	938.373us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otp_ctrl_tl_errors	7.330s	2468.224us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otp_ctrl_tl_errors	7.330s	2468.224us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otp_ctrl_csr_hw_reset	2.240s	137.065us	1	1	100.00
	otp_ctrl_csr_rw	2.260s	149.493us	5	5	100.00
	otp_ctrl_csr_aliasing	3.560s	163.064us	1	1	100.00
	otp_ctrl_same_csr_outstanding	2.970s	316.247us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otp_ctrl_csr_hw_reset	2.240s	137.065us	1	1	100.00
	otp_ctrl_csr_rw	2.260s	149.493us	5	5	100.00
	otp_ctrl_csr_aliasing	3.560s	163.064us	1	1	100.00
	otp_ctrl_same_csr_outstanding	2.970s	316.247us	5	5	100.00

V2S

632/660 passed

95.76 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
tl_intg_err				29	30	96.67
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
	otp_ctrl_tl_intg_err	23.610s	19951.110us	25	25	100.00
prim_count_check				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
prim_fsm_check				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_bus_integrity				25	25	100.00
	otp_ctrl_tl_intg_err	23.610s	19951.110us	25	25	100.00
sec_cm_secret_mem_scramble				10	10	100.00
	otp_ctrl_smoke	9.840s	624.617us	10	10	100.00
sec_cm_part_mem_digest				10	10	100.00
	otp_ctrl_smoke	9.840s	624.617us	10	10	100.00
sec_cm_dai_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_kdi_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_lci_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_part_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_scrmbl_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_timer_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_dai_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_kdi_seed_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_kdi_entropy_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_lci_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_part_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_scrmbl_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_timer_integ_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_timer_cnsty_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_timer_lfsr_redun				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_dai_fsm_local_esc				204	205	99.51
	otp_ctrl_parallel_lc_esc	26.410s	1799.010us	200	200	100.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_lci_fsm_local_esc				200	200	100.00
	otp_ctrl_parallel_lc_esc	26.410s	1799.010us	200	200	100.00
sec_cm_kdi_fsm_local_esc				200	200	100.00
	otp_ctrl_parallel_lc_esc	26.410s	1799.010us	200	200	100.00
sec_cm_part_fsm_local_esc				205	210	97.62
	otp_ctrl_parallel_lc_esc	26.410s	1799.010us	200	200	100.00
	otp_ctrl_macro_errs	25.360s	2771.930us	5	10	50.00
sec_cm_scrmbl_fsm_local_esc				200	200	100.00
	otp_ctrl_parallel_lc_esc	26.410s	1799.010us	200	200	100.00
sec_cm_timer_fsm_local_esc				204	205	99.51
	otp_ctrl_parallel_lc_esc	26.410s	1799.010us	200	200	100.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_dai_fsm_global_esc				204	205	99.51
	otp_ctrl_parallel_lc_esc	26.410s	1799.010us	200	200	100.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_lci_fsm_global_esc				200	200	100.00
	otp_ctrl_parallel_lc_esc	26.410s	1799.010us	200	200	100.00
sec_cm_kdi_fsm_global_esc				200	200	100.00
	otp_ctrl_parallel_lc_esc	26.410s	1799.010us	200	200	100.00
sec_cm_part_fsm_global_esc				205	210	97.62
	otp_ctrl_parallel_lc_esc	26.410s	1799.010us	200	200	100.00
	otp_ctrl_macro_errs	25.360s	2771.930us	5	10	50.00
sec_cm_scrmbl_fsm_global_esc				200	200	100.00
	otp_ctrl_parallel_lc_esc	26.410s	1799.010us	200	200	100.00
sec_cm_timer_fsm_global_esc				204	205	99.51
	otp_ctrl_parallel_lc_esc	26.410s	1799.010us	200	200	100.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_part_data_reg_integrity				300	300	100.00
	otp_ctrl_init_fail	7.720s	2619.830us	300	300	100.00
sec_cm_part_data_reg_bkgn_chk				28	50	56.00
	otp_ctrl_check_fail	30.170s	13161.057us	28	50	56.00
sec_cm_part_mem_regren				30	30	100.00
	otp_ctrl_dai_lock	58.210s	7295.285us	30	30	100.00
sec_cm_part_mem_sw_unreadable				30	30	100.00
	otp_ctrl_dai_lock	58.210s	7295.285us	30	30	100.00
sec_cm_part_mem_sw_unwritable				30	30	100.00
	otp_ctrl_dai_lock	58.210s	7295.285us	30	30	100.00
sec_cm_lc_part_mem_sw_noaccess				30	30	100.00
	otp_ctrl_dai_lock	58.210s	7295.285us	30	30	100.00
sec_cm_access_ctrl_mubi				30	30	100.00
	otp_ctrl_dai_lock	58.210s	7295.285us	30	30	100.00
sec_cm_token_valid_ctrl_mubi				10	10	100.00
	otp_ctrl_smoke	9.840s	624.617us	10	10	100.00
sec_cm_lc_ctrl_intersig_mubi				30	30	100.00
	otp_ctrl_dai_lock	58.210s	7295.285us	30	30	100.00
sec_cm_test_bus_lc_gated				10	10	100.00
	otp_ctrl_smoke	9.840s	624.617us	10	10	100.00
sec_cm_test_tl_lc_gate_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	235.390s	155421.431us	4	5	80.00
sec_cm_direct_access_config_regwen				30	30	100.00
	otp_ctrl_regwen	12.340s	5163.796us	30	30	100.00
sec_cm_check_trigger_config_regwen				10	10	100.00
	otp_ctrl_smoke	9.840s	624.617us	10	10	100.00
sec_cm_check_config_regwen				10	10	100.00
	otp_ctrl_smoke	9.840s	624.617us	10	10	100.00
sec_cm_macro_mem_integrity				5	10	50.00
	otp_ctrl_macro_errs	25.360s	2771.930us	5	10	50.00

26/101 passed

25.74 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
otp_ctrl_low_freq_read				1	1	100.00
	otp_ctrl_low_freq_read	15.180s	7937.677us	1	1	100.00
stress_all_with_rand_reset				25	100	25.00
	otp_ctrl_stress_all_with_rand_reset	189.380s	64336.155us	25	100	25.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.direct_access_rdata_				49 test runs
	otp_ctrl_check_fail	82360999098277651495087752752052688179167462940147009880180919840554507157930	1029	UVM_INFO @ 179642938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	11148620366637534594872507022307968262123054010417920747248120913763383952784	7146	UVM_INFO @ 982246714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	51290651963400826497154713585708054860053629879487628425078648814833831898802	2933	UVM_INFO @ 134704375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	60606882590418808090431625085902233903122115621951011437553888676961197418713	15017	UVM_INFO @ 2306271525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	9738341794441052869961186556957171410080407799421815845145496562350727521181	6285	UVM_INFO @ 2039898129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	9135243871537310888893729584974560817858621374045260659545700294605044815956	5086	UVM_INFO @ 1529752959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	85702661767536388219991275315831032750618721117580949230896221934717990406136	1986	UVM_INFO @ 2861725086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	63565238068103646928154060600213541109656462621998015393655790713512142431567	591	UVM_INFO @ 62413984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	45656336169938174576872343431355130233540133848108960175744741262600479895695	1932	UVM_INFO @ 2513734110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	97952817074984018065328601314864082430193731267540673210062855485466892136943	1255	UVM_INFO @ 133885760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	80616830302217116233674105360022791817550369736870125522707677557143684934741	12541	UVM_INFO @ 573478608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	73226271804585498648940045399018023548928024628653668116393439733589920812792	16633	UVM_INFO @ 57030937950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	26634300772105128549403697448308874219883148914119871916434266225758645561387	1017	UVM_INFO @ 887600915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	61871197867380647571049722076645954797212250573848028249521564387045637069423	23180	UVM_INFO @ 16459971582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	105361485839513348825289767776658700504188849884585042688797102461438148016824	187	UVM_INFO @ 145260720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	76079480377420020005449804507808087897533678310112565526164059851092026666092	3282	UVM_INFO @ 7996017644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	102322536985952310550917921608865250890731604074904746793817788240787206580830	3436	UVM_INFO @ 2343027583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	14982155019643609371782025753071996145473225742855312609627373421525733038650	2173	UVM_INFO @ 108231773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	35093214826515619172244761295427966336320627018406905247175884421080223156659	1367	UVM_INFO @ 321081626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	16325674562295607786346267447643293345435357912273173877634809728328023561838	9921	UVM_INFO @ 1748474084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	15945129385978807965584096623646848981308912809403005388180815452041338983189	115	UVM_INFO @ 195723258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	103369583216757050373425314203860787335686893122799892819172318843391664692313	273	UVM_INFO @ 260568629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	107009492887798325681100890976307110294239070310596883438936552313483842885277	3235	UVM_INFO @ 4196416672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	21915348339931076999650703464941984772709562476535834106610176164820495825564	9316	UVM_INFO @ 4198446338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	14702057174264222946730980804762510916244755243692449517366562592143548685722	1847	UVM_INFO @ 1200359163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	36111833557968541626571357346748543964808285868277281849628594482912524074173	14809	UVM_INFO @ 3859594354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	97403227524050093134594948834744457977546070130854989001602482525770222502956	7780	UVM_INFO @ 6022079750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	36936397207112116343336821172103856353371793760365347270657065091834942486967	1927	UVM_INFO @ 279083078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	46376032366916750418184988781350371589333232925817575867172419237123290724394	11859	UVM_INFO @ 1998360767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	112614690722406739397901574075251477729243414168641078888617380220350160543728	263	UVM_INFO @ 190979958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	58826720357762494196362865640139299403091582451441448704920994254035826029008	803	UVM_INFO @ 127866815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	80260300094664945610034727782593306564786982851953651816957439379691775534155	4832	UVM_INFO @ 714319716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	11934332619968885777797915613217153054830927280758862862373310251878044745875	8375	UVM_INFO @ 1115638862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	44947188469275510669513319634400631669967992074327268356792964987426753098240	541	UVM_INFO @ 1146565786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	31012423523172470125215998628117675481476844546368707861992089060816471030596	9739	UVM_INFO @ 13161057494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	48537626207611542548020299254841171904810105740983615859539443551395468137766	1742	UVM_INFO @ 4615158846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	101258203030887366110816866502490030877256074878440472699280823462657780626972	9779	UVM_INFO @ 1386340371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	44624336083957061612837657620751929439127897006833846512253724284547338154504	165	UVM_INFO @ 1886124940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	33721411189089794477621506504983140762262560194988186589317201084233797813791	18718	UVM_INFO @ 1443173346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	25395743678987429884823806773219467724051792032124706589104417327750445353816	5881	UVM_INFO @ 1509861768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	108138805112712438524169001293396594626629521148349056077352941578812920108191	1407	UVM_INFO @ 114227437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	90578378697482478445062717322945323106597124090739481358107740860766167203834	16500	UVM_INFO @ 9129294788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	3854520248067312541215920461911638196387395681201437730454705495774692820501	2234	UVM_INFO @ 6883489130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	94360231576109586712735221650503034218119152334616908860847483669155964349853	178	UVM_INFO @ 403653318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	106510052343014770102839318142825733952402293814672987950334093679948688879831	399	UVM_INFO @ 197043592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	92698706028753144922215244823719330600359295644660274068261465297848172675901	177	UVM_INFO @ 57062821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	44721385955927444503380397195067673273925588628225483912662121784402430173062	3343	UVM_INFO @ 15774686429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	15305885712693311858343562382776464440247041755603748705352439929105709594166	120	UVM_INFO @ 834872445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	70270364939804920385341152206749753809883023879710596995313352796048877312584	3459	UVM_INFO @ 2712418523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =				23 test runs
	otp_ctrl_stress_all_with_rand_reset	91119777101641209013068463033672272954150842009741618243345715086653509883764	3088	UVM_INFO @ 2013784929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	4718295833052701692241982721870797544564462250094078573723693809689397408492	92	UVM_INFO @ 53521092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	15885128444556359904260551315473083682826901104011027248449956976265897398244	23960	UVM_INFO @ 3724337040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	97401665469613412842251956403015294948129285664608314174410891763397536216552	2582	UVM_INFO @ 5967096686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	66618638724345263903229262987634971532221698623116203093019435881989238165903	92	UVM_INFO @ 33142794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	59310493734925114540845707066607976800938205669303911679148226616883363817826	2530	UVM_INFO @ 2122612575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	77898985728649914201198444555672919143571575013999570290216404105326043915295	140	UVM_INFO @ 4227251887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	11789298773810637482760333403441129304601994585460635451031859911497045151581	2697	UVM_INFO @ 6029549465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	3823176198058127749641594901557254679237526212419254292160783005360253330302	12938	UVM_INFO @ 1647585233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	30889617687779701614720215586029985873889731103903922516916432553164084893136	1750	UVM_INFO @ 73399478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	26071525844233362063169509922221779867389037467255090269635182885513377113036	144	UVM_INFO @ 6073376665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	83489114413026182090145460912262786806436964105901763748479201467997611213371	5122	UVM_INFO @ 230253711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	105705497708986194975412261849188562143688687723825149887221260626104065223528	8859	UVM_INFO @ 3264007776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	30336171889621914436944799300689907790512945159829291831299035797158776617602	4127	UVM_INFO @ 741113453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	80820667765227024616310395134758865175538567150879128359814620004792948056632	92	UVM_INFO @ 26558515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	67625097253812262156763470884060018751267446789116896699096185702704772986030	6215	UVM_INFO @ 706963088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	79290010121197262943547818670165426317065011196389862939003288554834358188707	92	UVM_INFO @ 102672628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	95565310075040772539394853583911722795432243662127488061272176130902862688665	25811	UVM_INFO @ 11472083978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	53270400112695495164456434188235941194460602551955484991667403011372206736821	3560	UVM_INFO @ 18012249560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	27982075793971771737506227494913656765381465639673465581844714277575929600315	16202	UVM_INFO @ 4044264743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	9077107809177976665338963920305236739407477352097663003342242469511364143176	92	UVM_INFO @ 106547429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	53868596510272095861088028407055301512476923446608987668570308790094073341180	3161	UVM_INFO @ 12891692629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	77501107315449693186253206684898056259035083036749365705741511308833072231491	92	UVM_INFO @ 34775606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =				14 test runs
	otp_ctrl_csr_mem_rw_with_rand_reset	110997032756602204345290219402848191539781648324702386310767366014030060779548	98	UVM_INFO @ 974409136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_csr_mem_rw_with_rand_reset	6510401745404106356465662261666931625661749567690021141072625087250567023681	92	UVM_INFO @ 107633175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	85612824985714926919052499315032099839856796066505146970496729503218548850038	1788	UVM_INFO @ 1049577094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	89596481869567756646137989002913574703310546099060484637784623129893628351940	4079	UVM_INFO @ 1730818501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	47736050948176819796805912544265648674305194756981490984079612265429886441681	92	UVM_INFO @ 107358954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	75555608769050940077944752931081193454767245899176016104677106647481519626596	1192	UVM_INFO @ 238655905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	101081453166975283284434137729393937602721304853769620991019560551586691423477	20613	UVM_INFO @ 814565034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	61643889986801211561547004886954179045079708260869049095702810861665441447059	139	UVM_INFO @ 14825186525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	41027577207524344534350235925991435101216264410833177710203727154412144571583	92	UVM_INFO @ 30205966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	64482393612693530938452210791308175675795303304741698032442154133520464164549	431	UVM_INFO @ 4456821222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	96916834644258282345507195625312896064538857447876167942876729009049285914972	188	UVM_INFO @ 1025341766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	94359534007316415983295657485313455473994960345677436689266135366886416270488	3054	UVM_INFO @ 4128291936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	11160634746804030882684100600216503531279179545777943766757304955780083807067	92	UVM_INFO @ 108109834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	63460403891368936531074841748918934396946391110878263157816851698651661705134	522	UVM_INFO @ 108501120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: otp_ctrl_core_reg_block.intr_state				13 test runs
	otp_ctrl_stress_all_with_rand_reset	115393117555964151444087722788797234285776070150451985518088850354134819842213	4499	UVM_INFO @ 2351089508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	6998823705245204438971022949158831776214628541751679162950018765485929417709	26030	UVM_INFO @ 24870187114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	3597741736749347653555848722510973812437474145936401740253933877844395258476	3908	UVM_INFO @ 6865556752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	35410680752221439203320371787052997465855609066499772425873144843826751925506	2312	UVM_INFO @ 3500978575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	109294644907603336321131894303611866967032166990753236989235316777999480139937	6283	UVM_INFO @ 10422642555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	45882554987362190720377755474806428515231779451934572443596033481663985978514	2099	UVM_INFO @ 1586432542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	79916969831102768970881652522272978838314089405380886013183482875307380960712	197	UVM_INFO @ 41474695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	79933779896653668867985217344898186675806416660210481747387871726814451124355	11613	UVM_INFO @ 22710627284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	85973107458702094558840923906682939238594151176111967207206543453456752623601	4291	UVM_INFO @ 9730404057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	93972986286602471664320326032106197595977624933201449657532362730994500552120	3608	UVM_INFO @ 6259368154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	89620470679998556685335987985797888380433599903504537823580834647715587081395	5339	UVM_INFO @ 14386621140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	98340939046314934547409606156752511253575298060046780322916097604586673069725	9224	UVM_INFO @ 29884184636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	107586379567489929676813140229394304998437575766763667346132478920409326961607	12638	UVM_INFO @ 16188458869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen				3 test runs
	otp_ctrl_stress_all_with_rand_reset	91328798753834090426199633709932516935719236402089693106049000225103247079407	11573	UVM_INFO @ 1511911891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	18492213214733618852544907849682043542275161581174782704172933581498842893424	2998	UVM_INFO @ 1219418159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	31416597393050473148354274664851215484093006507281161123868499152156050884184	5962	UVM_INFO @ 2009813075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [otp_ctrl_common_vseq] wait timeout occurred!				1 test run
	otp_ctrl_sec_cm	32736833907625950678510626772733394845896129753010525763100708011806090947006	102	UVM_INFO @ 10096316829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr rdata* readout mismatch				1 test run
	otp_ctrl_stress_all_with_rand_reset	6256835691031043978253352891459399768154803388561896298368262979169534285331	2568	UVM_INFO @ 14916299034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value:				1 test run
	otp_ctrl_stress_all_with_rand_reset	75937162408715067660820278826700879694322634469711261146291081381906453053327	25638	UVM_INFO @ 54250300737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	otp_ctrl_stress_all_with_rand_reset	57183257346227431263653773059838368677900541125225429856569894350601726891505	32685	UVM_INFO @ 64336154945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---