Simulation Results: rom_ctrl/32kb

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.31%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 8.480s 174.363us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.420s 566.889us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 6.040s 166.386us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.700s 8195.686us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.350s 168.708us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.700s 2232.254us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 6.040s 166.386us 5 5 100.00
rom_ctrl_csr_aliasing 5.350s 168.708us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.810s 555.500us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.220s 454.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.080s 320.561us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 32.310s 2131.574us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 11.390s 308.751us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 7.150s 164.727us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 12.800s 422.210us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 12.800s 422.210us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.420s 566.889us 1 1 100.00
rom_ctrl_csr_rw 6.040s 166.386us 5 5 100.00
rom_ctrl_csr_aliasing 5.350s 168.708us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.610s 128.126us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.420s 566.889us 1 1 100.00
rom_ctrl_csr_rw 6.040s 166.386us 5 5 100.00
rom_ctrl_csr_aliasing 5.350s 168.708us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.610s 128.126us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 153.710s 8900.548us 19 20 95.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.060s 1573.522us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 260.660s 3408.451us 5 5 100.00
rom_ctrl_tl_intg_err 83.740s 1325.886us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 260.660s 3408.451us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 260.660s 3408.451us 5 5 100.00
sec_cm_checker_ctr_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 153.710s 8900.548us 19 20 95.00
sec_cm_checker_ctrl_flow_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 153.710s 8900.548us 19 20 95.00
sec_cm_checker_fsm_local_esc 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 153.710s 8900.548us 19 20 95.00
sec_cm_compare_ctrl_flow_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 153.710s 8900.548us 19 20 95.00
sec_cm_compare_ctr_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 153.710s 8900.548us 19 20 95.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 260.660s 3408.451us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 260.660s 3408.451us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 8.480s 174.363us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 8.480s 174.363us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 8.480s 174.363us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 83.740s 1325.886us 25 25 100.00
sec_cm_bus_local_esc 21 22 95.45
rom_ctrl_corrupt_sig_fatal_chk 153.710s 8900.548us 19 20 95.00
rom_ctrl_kmac_err_chk 11.390s 308.751us 2 2 100.00
sec_cm_mux_mubi 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 153.710s 8900.548us 19 20 95.00
sec_cm_mux_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 153.710s 8900.548us 19 20 95.00
sec_cm_ctrl_redun 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 153.710s 8900.548us 19 20 95.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.060s 1573.522us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 260.660s 3408.451us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 445.940s 4543.289us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 48832088332045899900241505460722822979763132950058013986488680486679317751910 78
UVM_INFO @ 95563849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---