Simulation Results: rom_ctrl/64kb

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.51 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.05 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 9.430s 225.027us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 12.660s 1074.838us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 12.590s 300.368us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 8.840s 357.765us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.940s 2396.737us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 10.000s 822.620us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 12.590s 300.368us 5 5 100.00
rom_ctrl_csr_aliasing 6.940s 2396.737us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 10.040s 727.396us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 9.090s 384.043us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 14.920s 295.859us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 61.100s 7960.173us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 20.370s 382.516us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 11.770s 297.296us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 19.580s 1021.315us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 19.580s 1021.315us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 12.660s 1074.838us 1 1 100.00
rom_ctrl_csr_rw 12.590s 300.368us 5 5 100.00
rom_ctrl_csr_aliasing 6.940s 2396.737us 1 1 100.00
rom_ctrl_same_csr_outstanding 15.680s 355.300us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 12.660s 1074.838us 1 1 100.00
rom_ctrl_csr_rw 12.590s 300.368us 5 5 100.00
rom_ctrl_csr_aliasing 6.940s 2396.737us 1 1 100.00
rom_ctrl_same_csr_outstanding 15.680s 355.300us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 330.280s 28066.302us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 65.930s 1563.356us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 619.470s 2586.641us 5 5 100.00
rom_ctrl_tl_intg_err 161.910s 441.283us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 619.470s 2586.641us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 619.470s 2586.641us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 330.280s 28066.302us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 330.280s 28066.302us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 330.280s 28066.302us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 330.280s 28066.302us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 330.280s 28066.302us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 619.470s 2586.641us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 619.470s 2586.641us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 9.430s 225.027us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 9.430s 225.027us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 9.430s 225.027us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 161.910s 441.283us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 330.280s 28066.302us 20 20 100.00
rom_ctrl_kmac_err_chk 20.370s 382.516us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 330.280s 28066.302us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 330.280s 28066.302us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 330.280s 28066.302us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 65.930s 1563.356us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 619.470s 2586.641us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 280.970s 3753.243us 20 20 100.00