| V1 |
|
100.00% |
| V2 |
|
85.83% |
| V2S |
|
100.00% |
| V3 |
|
47.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 1.780s | 337.746us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.930s | 18.316us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rv_timer_csr_rw | 0.940s | 14.364us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 1.790s | 151.529us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 1.200s | 42.754us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.330s | 22.271us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rv_timer_csr_rw | 0.940s | 14.364us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.200s | 42.754us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 2 | 20 | 10.00 | |||
| rv_timer_random_reset | 8.410s | 6301.107us | 2 | 20 | 10.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 6.730s | 2893.769us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 758.460s | 1643025.813us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 758.460s | 1643025.813us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 8.970s | 13366.700us | 20 | 20 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rv_timer_alert_test | 0.930s | 26.386us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| rv_timer_intr_test | 0.970s | 46.419us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.170s | 146.471us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.170s | 146.471us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.930s | 18.316us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.940s | 14.364us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.200s | 42.754us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.200s | 133.669us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.930s | 18.316us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.940s | 14.364us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.200s | 42.754us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.200s | 133.669us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rv_timer_sec_cm | 1.160s | 205.751us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.880s | 143.156us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.880s | 143.156us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 4 | 10 | 40.00 | |||
| rv_timer_min | 1.450s | 2197.978us | 4 | 10 | 40.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 0.970s | 44.653us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 15 | 20 | 75.00 | |||
| rv_timer_stress_all_with_rand_reset | 61.420s | 23674.989us | 15 | 20 | 75.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 24 test runs | |||
| rv_timer_random_reset | 22252469774341038172121538824424664646853971096741137521830255612438178285686 | 75 |
UVM_INFO @ 248835570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 40094965644666643720477916342898159410874320965561368209090384632347212037093 | 75 |
UVM_INFO @ 225698857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 65576991713983995745478521801450608576142201817785607119965859030177332428998 | 77 |
UVM_INFO @ 417510768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 32426626683732351464880286390371050374598877309266106071399231367357517964378 | 76 |
UVM_INFO @ 65230318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 14485063454326607661151922181628773720694275638048543398495421656932131130495 | 75 |
UVM_INFO @ 169783355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 78873459563007990288856322451808339534082659882507249198103115616133990427344 | 77 |
UVM_INFO @ 2197978476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 17951659937149577939659727621278332412772896785689863896646155370586534483579 | 75 |
UVM_INFO @ 149235882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 43276760023653235182226602587299997478780616023037943879772699931366034807421 | 75 |
UVM_INFO @ 6301107367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 66617155278414144869393326476111772814383451222834008502702980686154849463784 | 75 |
UVM_INFO @ 354925923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 51302831779474435624739351479838734833165771893863977635682225304423684486906 | 75 |
UVM_INFO @ 74810006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 54438545381707685421180471185548163893484616684598559951273306395905459441688 | 75 |
UVM_INFO @ 659600637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 60319308054708440450943108644593023345861774399276763494201782498063904448559 | 75 |
UVM_INFO @ 313681415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 43160791458614578540977293976042428068105846758579541555350489618781662704640 | 75 |
UVM_INFO @ 205739856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 4434719500151393294394427143328163230396182164375970683844437420107142681959 | 75 |
UVM_INFO @ 55780144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 81399108961829965759809874603233749318193030286310482465079181981488948158123 | 75 |
UVM_INFO @ 129193338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 41475462255965269155098189323440523507159571335203496268845368987985786439516 | 77 |
UVM_INFO @ 165749614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 15527464200776384422585816671618939078629402672495413559452240406166272513967 | 75 |
UVM_INFO @ 271759206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 65760486229011810669401631395118926623682981413516189037668366836559356095099 | 75 |
UVM_INFO @ 113845288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 68132543157011389601366516316594735024050540662065355307168437353170813732409 | 75 |
UVM_INFO @ 64060679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 59720173046815649680103810338201862905986840778376789323372872138719445526011 | 75 |
UVM_INFO @ 62925539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 101401802861956777525826685363714006780595862015705899189171486554684061280744 | 75 |
UVM_INFO @ 266563656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 18000532100550742324028198377314959801443030977225541452445321310979937830062 | 75 |
UVM_INFO @ 9798836190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 65753100789433786183612522863305251812011179565746842714042371171347071783048 | 75 |
UVM_INFO @ 232537157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 42412186530060853649147856309127854878617341601562380422203896356274058705706 | 75 |
UVM_INFO @ 110113107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 9 test runs | |||
| rv_timer_max | 68960802404926475440499159680110657373415445318242166656225202260275978784557 | 75 |
UVM_INFO @ 170174833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 105068336733046548213991096561590165931984827135680064713152241330222325656208 | 75 |
UVM_INFO @ 197034017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 79405815678864371568463289947593253888693501626156746827401530971051698846598 | 76 |
UVM_INFO @ 45173648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 87187864278947622206070848277814166234960260237456002633796632158183161740241 | 75 |
UVM_INFO @ 44555353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 64172745495953105832047523302449604622753553688447820607303233885533440702106 | 75 |
UVM_INFO @ 43375103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 56985008572597667888603699685099398468788930915963280624278829278257748014466 | 75 |
UVM_INFO @ 65391872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 28944485152253096306952895327063202646608062625350018713501092134015233434359 | 76 |
UVM_INFO @ 219053327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 23691004799684818602273632377770936611456004128240502389894407132412415007957 | 75 |
UVM_INFO @ 181359617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 34851582239874482056900921286071992928809805531538491227171900223925526208861 | 75 |
UVM_INFO @ 49487859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) | 3 test runs | |||
| rv_timer_stress_all_with_rand_reset | 36307023971818873084646835249349024025357120916859688547858716362122479137517 | 91 |
UVM_INFO @ 180734272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 9911883692435124748470784822834715818910005257930554527278705583711878146652 | 261 |
UVM_INFO @ 2954220539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 100435758435451559489495317801965330116911276898039223287476686558549158517632 | 143 |
UVM_INFO @ 2631598724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 2 test runs | |||
| rv_timer_stress_all_with_rand_reset | 12283965810475820067740500713320341643878925598319865368769352078483200946297 | 123 |
UVM_INFO @ 1483475943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 61404183998891055572684239780990958828236381935984962255896131670350698635674 | 125 |
UVM_INFO @ 3100857634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) | 1 test run | |||
| rv_timer_max | 115626788596014591695621313358408922401253351318930905707486218501055325123112 | 75 |
UVM_INFO @ 44652913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|