Simulation Results: spi_device/2p

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.96 %
  • code
  • 94.21 %
  • assert
  • 94.62 %
  • func
  • 99.06 %
  • line
  • 98.95 %
  • branch
  • 98.37 %
  • cond
  • 96.61 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
97.50%
V2
99.72%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 24 25 96.00
spi_device_flash_and_tpm 522.720s 65256.432us 24 25 96.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.480s 51.774us 1 1 100.00
csr_rw 5 5 100.00
spi_device_csr_rw 2.990s 171.787us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 21.400s 1631.369us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 7.780s 442.481us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_device_csr_mem_rw_with_rand_reset 4.670s 692.326us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_device_csr_rw 2.990s 171.787us 5 5 100.00
spi_device_csr_aliasing 7.780s 442.481us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.090s 17.609us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.350s 231.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 15 15 100.00
spi_device_csb_read 1.280s 39.109us 15 15 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.600s 108.258us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 1.160s 30.856us 1 1 100.00
tpm_read 15 15 100.00
spi_device_tpm_rw 8.590s 193.542us 15 15 100.00
tpm_write 15 15 100.00
spi_device_tpm_rw 8.590s 193.542us 15 15 100.00
tpm_hw_reg 30 30 100.00
spi_device_tpm_read_hw_reg 25.130s 19867.011us 15 15 100.00
spi_device_tpm_sts_read 1.380s 89.974us 15 15 100.00
tpm_fully_random_case 15 15 100.00
spi_device_tpm_all 41.280s 22768.541us 15 15 100.00
pass_cmd_filtering 40 40 100.00
spi_device_pass_cmd_filtering 14.740s 18414.223us 15 15 100.00
spi_device_flash_all 285.490s 109865.056us 25 25 100.00
pass_addr_translation 40 40 100.00
spi_device_pass_addr_payload_swap 41.350s 13528.329us 15 15 100.00
spi_device_flash_all 285.490s 109865.056us 25 25 100.00
pass_payload_translation 40 40 100.00
spi_device_pass_addr_payload_swap 41.350s 13528.329us 15 15 100.00
spi_device_flash_all 285.490s 109865.056us 25 25 100.00
cmd_info_slots 25 25 100.00
spi_device_flash_all 285.490s 109865.056us 25 25 100.00
cmd_read_status 40 40 100.00
spi_device_intercept 18.470s 4623.007us 15 15 100.00
spi_device_flash_all 285.490s 109865.056us 25 25 100.00
cmd_read_jedec 40 40 100.00
spi_device_intercept 18.470s 4623.007us 15 15 100.00
spi_device_flash_all 285.490s 109865.056us 25 25 100.00
cmd_read_sfdp 40 40 100.00
spi_device_intercept 18.470s 4623.007us 15 15 100.00
spi_device_flash_all 285.490s 109865.056us 25 25 100.00
cmd_fast_read 40 40 100.00
spi_device_intercept 18.470s 4623.007us 15 15 100.00
spi_device_flash_all 285.490s 109865.056us 25 25 100.00
cmd_read_pipeline 40 40 100.00
spi_device_intercept 18.470s 4623.007us 15 15 100.00
spi_device_flash_all 285.490s 109865.056us 25 25 100.00
flash_cmd_upload 15 15 100.00
spi_device_upload 13.330s 2492.758us 15 15 100.00
mailbox_command 15 15 100.00
spi_device_mailbox 75.680s 25118.320us 15 15 100.00
mailbox_cross_outside_command 15 15 100.00
spi_device_mailbox 75.680s 25118.320us 15 15 100.00
mailbox_cross_inside_command 15 15 100.00
spi_device_mailbox 75.680s 25118.320us 15 15 100.00
cmd_read_buffer 30 30 100.00
spi_device_flash_mode 28.850s 5460.645us 15 15 100.00
spi_device_read_buffer_direct 14.910s 3967.921us 15 15 100.00
cmd_dummy_cycle 40 40 100.00
spi_device_mailbox 75.680s 25118.320us 15 15 100.00
spi_device_flash_all 285.490s 109865.056us 25 25 100.00
quad_spi 25 25 100.00
spi_device_flash_all 285.490s 109865.056us 25 25 100.00
dual_spi 25 25 100.00
spi_device_flash_all 285.490s 109865.056us 25 25 100.00
4b_3b_feature 15 15 100.00
spi_device_cfg_cmd 16.860s 6409.794us 15 15 100.00
write_enable_disable 15 15 100.00
spi_device_cfg_cmd 16.860s 6409.794us 15 15 100.00
TPM_with_flash_or_passthrough_mode 24 25 96.00
spi_device_flash_and_tpm 522.720s 65256.432us 24 25 96.00
tpm_and_flash_trans_with_min_inactive_time 25 25 100.00
spi_device_flash_and_tpm_min_idle 569.170s 307310.711us 25 25 100.00
stress_all 15 15 100.00
spi_device_stress_all 652.100s 75571.756us 15 15 100.00
alert_test 10 10 100.00
spi_device_alert_test 1.220s 32.649us 10 10 100.00
intr_test 10 10 100.00
spi_device_intr_test 1.180s 44.941us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_device_tl_errors 6.290s 1410.070us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_device_tl_errors 6.290s 1410.070us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_device_csr_hw_reset 1.480s 51.774us 1 1 100.00
spi_device_csr_rw 2.990s 171.787us 5 5 100.00
spi_device_csr_aliasing 7.780s 442.481us 1 1 100.00
spi_device_same_csr_outstanding 4.740s 255.926us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_device_csr_hw_reset 1.480s 51.774us 1 1 100.00
spi_device_csr_rw 2.990s 171.787us 5 5 100.00
spi_device_csr_aliasing 7.780s 442.481us 1 1 100.00
spi_device_same_csr_outstanding 4.740s 255.926us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_device_sec_cm 1.830s 1928.150us 5 5 100.00
spi_device_tl_intg_err 26.940s 4288.158us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
spi_device_tl_intg_err 26.940s 4288.158us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 15 15 100.00
spi_device_flash_mode_ignore_cmds 287.830s 228917.918us 15 15 100.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp * 1 test run
spi_device_flash_and_tpm 45043257654606968138158227451568100136202629799127667978639288378669311110408 93
tl_ul_fuzzy_flash_status_q[i] = 0xf4e4a8
tl_ul_fuzzy_flash_status_q[i] = 0x1c1b8a
tl_ul_fuzzy_flash_status_q[i] = 0x1c1b8a
tl_ul_fuzzy_flash_status_q[i] = 0x65ad76