Simulation Results: spi_host

 
24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.82 %
  • code
  • 95.06 %
  • assert
  • 95.64 %
  • func
  • 90.76 %
  • block
  • 97.00 %
  • line
  • 98.76 %
  • branch
  • 93.45 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.87%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 157.000s 20987.877us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 25.599us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 52.269us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 164.544us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 225.524us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 3.000s 36.998us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 52.269us 5 5 100.00
spi_host_csr_aliasing 1.000s 225.524us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 39.400us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 16.505us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 48.820us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 7.000s 522.662us 10 10 100.00
spi_host_error_cmd 2.000s 78.228us 10 10 100.00
spi_host_event 171.000s 23190.759us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 9.000s 507.615us 10 10 100.00
speed 10 10 100.00
spi_host_speed 9.000s 507.615us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 9.000s 507.615us 10 10 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 92.000s 2783.878us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 46.711us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 9.000s 507.615us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 9.000s 507.615us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 157.000s 20987.877us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 157.000s 20987.877us 10 10 100.00
stress_all 9 10 90.00
spi_host_stress_all 56.000s 1708.195us 9 10 90.00
spien 10 10 100.00
spi_host_spien 7.000s 1833.807us 10 10 100.00
stall 9 10 90.00
spi_host_status_stall 1368.000s 566172.220us 9 10 90.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 14.000s 9005.888us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 7.000s 522.662us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 17.333us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 18.352us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 414.474us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 414.474us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 25.599us 1 1 100.00
spi_host_csr_rw 2.000s 52.269us 5 5 100.00
spi_host_csr_aliasing 1.000s 225.524us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 24.381us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 25.599us 1 1 100.00
spi_host_csr_rw 2.000s 52.269us 5 5 100.00
spi_host_csr_aliasing 1.000s 225.524us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 24.381us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 318.588us 25 25 100.00
spi_host_sec_cm 2.000s 72.677us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 318.588us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 5 5 100.00
spi_host_upper_range_clkdiv 142.000s 9427.486us 5 5 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/reseed_opt/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed 1 test run
spi_host_status_stall 74158345753168774131690015331038691412926902730898506633361447369130519225157 4508
UVM_ERROR @ 144039298704 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=144039299000 ps
UVM_INFO @ 144039298704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_stress_all 35719530427663708657985009602389517866178485761962712609021667790773396038035 367
UVM_INFO @ 17101384994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---