Simulation Results

Simulation Results: sysrst_ctrl

24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
95.18 %

code
97.74 %

assert
97.80 %

func
90.01 %

line
99.24 %

branch
99.30 %

cond
97.86 %

toggle
100.00 %

FSM
92.31 %

Validation stages

V1		100.00%
V2		97.01%
V2S		100.00%
V3		90.00%

43/43 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	sysrst_ctrl_smoke	7.950s	2112.079us	10	10	100.00
input_output_inverted				10	10	100.00
	sysrst_ctrl_in_out_inverted	11.190s	2495.817us	10	10	100.00
combo_detect_ec_rst				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst	8.900s	2158.338us	5	5	100.00
combo_detect_ec_rst_with_pre_cond				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	9.090s	2337.237us	5	5	100.00
csr_hw_reset				1	1	100.00
	sysrst_ctrl_csr_hw_reset	10.730s	4012.121us	1	1	100.00
csr_rw				5	5	100.00
	sysrst_ctrl_csr_rw	6.580s	2034.158us	5	5	100.00
csr_bit_bash				1	1	100.00
	sysrst_ctrl_csr_bit_bash	71.760s	23496.608us	1	1	100.00
csr_aliasing				1	1	100.00
	sysrst_ctrl_csr_aliasing	6.850s	3180.687us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	8.290s	2063.558us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	sysrst_ctrl_csr_rw	6.580s	2034.158us	5	5	100.00
	sysrst_ctrl_csr_aliasing	6.850s	3180.687us	1	1	100.00

324/334 passed

97.01 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				25	25	100.00
	sysrst_ctrl_combo_detect	448.560s	164418.156us	25	25	100.00
combo_detect_with_pre_cond				91	100	91.00
	sysrst_ctrl_combo_detect_with_pre_cond	476.910s	198512.238us	91	100	91.00
auto_block_key_outputs				25	25	100.00
	sysrst_ctrl_auto_blk_key_output	54.240s	104038.371us	25	25	100.00
keyboard_input_triggered_interrupt				50	50	100.00
	sysrst_ctrl_edge_detect	957.130s	1625429.478us	50	50	100.00
pin_output_keyboard_inversion_control				10	10	100.00
	sysrst_ctrl_pin_override_test	9.720s	2510.457us	10	10	100.00
pin_input_value_accessibility				10	10	100.00
	sysrst_ctrl_pin_access_test	7.440s	2046.187us	10	10	100.00
ec_power_on_reset				10	10	100.00
	sysrst_ctrl_ec_pwr_on_rst	1454.660s	1364875.206us	10	10	100.00
flash_write_protect_output				10	10	100.00
	sysrst_ctrl_flash_wr_prot_out	9.600s	2609.549us	10	10	100.00
ultra_low_power_test				24	25	96.00
	sysrst_ctrl_ultra_low_pwr	37.650s	991597.848us	24	25	96.00
sysrst_ctrl_feature_disable				2	2	100.00
	sysrst_ctrl_feature_disable	58.430s	29259.491us	2	2	100.00
stress_all				10	10	100.00
	sysrst_ctrl_stress_all	375.580s	165769.324us	10	10	100.00
alert_test				10	10	100.00
	sysrst_ctrl_alert_test	8.090s	2013.811us	10	10	100.00
intr_test				10	10	100.00
	sysrst_ctrl_intr_test	7.390s	2012.653us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	sysrst_ctrl_tl_errors	10.290s	2045.966us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	sysrst_ctrl_tl_errors	10.290s	2045.966us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	10.730s	4012.121us	1	1	100.00
	sysrst_ctrl_csr_rw	6.580s	2034.158us	5	5	100.00
	sysrst_ctrl_csr_aliasing	6.850s	3180.687us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	13.940s	9699.792us	5	5	100.00
tl_d_partial_access				12	12	100.00
	sysrst_ctrl_csr_hw_reset	10.730s	4012.121us	1	1	100.00
	sysrst_ctrl_csr_rw	6.580s	2034.158us	5	5	100.00
	sysrst_ctrl_csr_aliasing	6.850s	3180.687us	1	1	100.00
	sysrst_ctrl_same_csr_outstanding	13.940s	9699.792us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	sysrst_ctrl_sec_cm	109.830s	42010.783us	5	5	100.00
	sysrst_ctrl_tl_intg_err	102.760s	42370.923us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	sysrst_ctrl_tl_intg_err	102.760s	42370.923us	25	25	100.00

9/10 passed

90.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				9	10	90.00
	sysrst_ctrl_stress_all_with_rand_reset	23.910s	6408.072us	9	10	90.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [] vs [*])				3 test runs
	sysrst_ctrl_combo_detect_with_pre_cond	31123780845663907320298372797116890789661130937379595778038531957622047320550	704	UVM_INFO @ 66440662554 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 66460662554 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 76535409179 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2e UVM_INFO @ 76535631401 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x25
	sysrst_ctrl_combo_detect_with_pre_cond	17111617916637354699621500368511323717699525350252417608998029095931282804231	674	UVM_ERROR @ 24404925211 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 24404925211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	9076407420857913763582184092970796447776062884503924089164739258231556738760	668	UVM_ERROR @ 13863115365 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 13863115365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-*				2 test runs
	sysrst_ctrl_combo_detect_with_pre_cond	42206120932308021818571038501065400559287585236861418617387655934963181075357	706	UVM_INFO @ 49969053739 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 49989053739 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 60066566081 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2e UVM_INFO @ 60066715503 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xd
	sysrst_ctrl_combo_detect_with_pre_cond	79050231719704351203459818594559499512738562678985451278986754841240288869213	672	UVM_INFO @ 26562318067 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x27 UVM_INFO @ 26562818070 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2d UVM_INFO @ 27143217974 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0 UVM_INFO @ 27158217974 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1e
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:184) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == * (* [] vs [*])				1 test run
	sysrst_ctrl_stress_all_with_rand_reset	86178024894646898210038864122374485214898305121750372498992251312055051198521	730	UVM_INFO @ 18173137159 ps: (cip_base_vseq.sv:1173) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Stress w/ reset is done for run 10/10 UVM_INFO @ 18198694784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)				1 test run
	sysrst_ctrl_ultra_low_pwr	48587902492565988566407734789387866372310611708579018456140623385995908563943	657	UVM_INFO @ 2339637759 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i UVM_INFO @ 7399637759 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i UVM_INFO @ 9994637759 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 10014464533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [] vs [*])				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	82999457413655253359397000822074216433993760821846797964899867202899834293630	670	UVM_INFO @ 14205466206 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 14225466206 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_ERROR @ 14340495156 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 8 [0x8]) UVM_INFO @ 14340495156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(8) vs exp(3) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	83311962694771828697469512494052216599233106754777923653297055508006825784791	667	UVM_ERROR @ 13098980568 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-4 UVM_INFO @ 13098980568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(9) vs exp(5) +/-*				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	7255982474003529242916524348292439496345511007618499236548186886099702263191	667	UVM_INFO @ 12706990834 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:152) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_h2l_expected == 0 UVM_INFO @ 12896990834 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 12916990834 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 22931191701 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [] vs [*])				1 test run
	sysrst_ctrl_combo_detect_with_pre_cond	36534527944270084541202073926923518895272176325636684142894183538626867750832	713	UVM_INFO @ 95729193112 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x30 UVM_INFO @ 95729213946 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x29 UVM_INFO @ 96178874168 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3 UVM_INFO @ 96193748302 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1b