Simulation Results

Simulation Results: uart

24/05/2026 04:19:36 DVSim: v1.49.0 sha: 32edacb json Branch: reseed_opt Tool: vcs [unknown]

Coverage statistics

Total
97.75 %

code
96.86 %

assert
97.12 %

func
99.28 %

line
99.48 %

branch
98.14 %

cond
98.25 %

toggle
91.55 %

Validation stages

V1		100.00%
V2		97.23%
V2S		100.00%
V3		75.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	uart_smoke	18.230s	5765.573us	10	10	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.770s	15.678us	1	1	100.00
csr_rw				5	5	100.00
	uart_csr_rw	0.980s	29.161us	5	5	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	2.910s	376.420us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.900s	23.603us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	uart_csr_mem_rw_with_rand_reset	1.550s	24.168us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	uart_csr_rw	0.980s	29.161us	5	5	100.00
	uart_csr_aliasing	0.900s	23.603us	1	1	100.00

386/397 passed

97.23 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				10	10	100.00
	uart_tx_rx	276.370s	110213.782us	10	10	100.00
parity				20	20	100.00
	uart_smoke	18.230s	5765.573us	10	10	100.00
	uart_tx_rx	276.370s	110213.782us	10	10	100.00
parity_error				20	20	100.00
	uart_intr	183.790s	296454.170us	10	10	100.00
	uart_rx_parity_err	336.560s	398520.045us	10	10	100.00
watermark				20	20	100.00
	uart_tx_rx	276.370s	110213.782us	10	10	100.00
	uart_intr	183.790s	296454.170us	10	10	100.00
fifo_full				10	10	100.00
	uart_fifo_full	285.830s	253150.307us	10	10	100.00
fifo_overflow				10	10	100.00
	uart_fifo_overflow	304.270s	209431.501us	10	10	100.00
fifo_reset				200	200	100.00
	uart_fifo_reset	588.610s	76292.041us	200	200	100.00
rx_frame_err				10	10	100.00
	uart_intr	183.790s	296454.170us	10	10	100.00
rx_break_err				10	10	100.00
	uart_intr	183.790s	296454.170us	10	10	100.00
rx_timeout				10	10	100.00
	uart_intr	183.790s	296454.170us	10	10	100.00
perf				10	10	100.00
	uart_perf	1031.960s	26729.143us	10	10	100.00
sys_loopback				10	10	100.00
	uart_loopback	20.200s	8743.149us	10	10	100.00
line_loopback				10	10	100.00
	uart_loopback	20.200s	8743.149us	10	10	100.00
rx_noise_filter				2	10	20.00
	uart_noise_filter	105.410s	40112.926us	2	10	20.00
rx_start_bit_filter				10	10	100.00
	uart_rx_start_bit_filter	59.930s	38758.747us	10	10	100.00
tx_overide				10	10	100.00
	uart_tx_ovrd	25.960s	5892.341us	10	10	100.00
rx_oversample				10	10	100.00
	uart_rx_oversample	22.540s	6057.240us	10	10	100.00
long_b2b_transfer				10	10	100.00
	uart_long_xfer_wo_dly	752.780s	135609.864us	10	10	100.00
stress_all				7	10	70.00
	uart_stress_all	1450.310s	241092.183us	7	10	70.00
alert_test				10	10	100.00
	uart_alert_test	0.950s	14.877us	10	10	100.00
intr_test				10	10	100.00
	uart_intr_test	0.960s	20.733us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	uart_tl_errors	2.690s	245.014us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	uart_tl_errors	2.690s	245.014us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	uart_csr_hw_reset	0.770s	15.678us	1	1	100.00
	uart_csr_rw	0.980s	29.161us	5	5	100.00
	uart_csr_aliasing	0.900s	23.603us	1	1	100.00
	uart_same_csr_outstanding	1.150s	29.899us	5	5	100.00
tl_d_partial_access				12	12	100.00
	uart_csr_hw_reset	0.770s	15.678us	1	1	100.00
	uart_csr_rw	0.980s	29.161us	5	5	100.00
	uart_csr_aliasing	0.900s	23.603us	1	1	100.00
	uart_same_csr_outstanding	1.150s	29.899us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	uart_sec_cm	1.330s	165.209us	5	5	100.00
	uart_tl_intg_err	1.740s	110.286us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	uart_tl_intg_err	1.740s	110.286us	25	25	100.00

15/20 passed

75.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				15	20	75.00
	uart_stress_all_with_rand_reset	72.900s	75033.012us	15	20	75.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				9 test runs
	uart_noise_filter	60231261110886202133481588813156750140985773921319632726271824659566636031348	80	UVM_ERROR @ 39716875552 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 40018653028 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 40018653028 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 40104966073 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
	uart_stress_all	74777655003627265796436108645059683013247638837718845901419594391932161951356	115	UVM_ERROR @ 577291331594 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 577291644094 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 577291956594 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 577292269094 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	49240661669035935540989189537756489119004972104943078144778742087031343321812	79	UVM_ERROR @ 10190268692 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 10191708692 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 10192428692 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 10193148692 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	1076710415015310268456802709720313752617559394245783968448918362033687449255	75	UVM_ERROR @ 8629507058 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_INFO @ 25659320192 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/11 UVM_ERROR @ 26134314023 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 16, clk_pulses: 0 UVM_ERROR @ 26134332542 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	3692986606754782599367742820427645466319411455808701987126243390864391850874	74	UVM_ERROR @ 16994617 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 241761854 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr UVM_ERROR @ 241761854 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr UVM_ERROR @ 241761854 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
	uart_noise_filter	85261636462156592523095009802411056671662761525237264087794629210617561206707	76	UVM_ERROR @ 696785645 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 697663189 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 717458949 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 717479357 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_stress_all_with_rand_reset	110605306100517727960764876026325766873671798418210715532191577123427108406395	109	UVM_ERROR @ 1155216740 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_INFO @ 1159811500 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/236 UVM_ERROR @ 1160662882 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 1170352420 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all_with_rand_reset	26907830295210396245383477970352394641980881455403631920421907816281331219180	87	UVM_ERROR @ 505140654 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 546703320 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 589702116 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0 UVM_ERROR @ 589723392 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (115 [0x73] vs 119 [0x77]) reg name: uart_reg_block.rdata
	uart_stress_all_with_rand_reset	20799905048655062419826318257774821659051799023389369432083571060744685963204	203	UVM_ERROR @ 8422802742 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 8422802742 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 8428761878 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 8428761878 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:				4 test runs
	uart_noise_filter	104413022574778774372495680302776635004878067999831429415147029766074971785179	76	UVM_ERROR @ 37481026240 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 37481085064 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 174 [0xae]) reg name: uart_reg_block.rdata UVM_ERROR @ 37609262560 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 9, clk_pulses: 0 UVM_ERROR @ 37609321384 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	77858563262690444402946646702124736257978404214690574121081919128874692298109	75	UVM_ERROR @ 1914570502 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 1914581140 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (80 [0x50] vs 239 [0xef]) reg name: uart_reg_block.rdata UVM_ERROR @ 2116075498 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 2116086136 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	113462470915564364501992202569785489788591131782264629071828707233705199595659	76	UVM_ERROR @ 11949063722 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 11949100759 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (14 [0xe] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 12059767315 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 12059767315 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
	uart_stress_all_with_rand_reset	115359895552484806735616661743531874962764000037114249261942396733485573942084	124	UVM_ERROR @ 1570210040 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 1570222540 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 1570235040 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 1570247540 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [] vs []) check rx_empty fail: uart_rx_clk_pulses = , rx_q.size = *				3 test runs
	uart_stress_all	61500943332630881655300058719033128730438578163309353718626848224025622849962	100	UVM_ERROR @ 354587968551 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 15, clk_pulses: 0 UVM_ERROR @ 354588254265 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (132 [0x84] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 354588397122 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 354588539979 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (132 [0x84] vs 255 [0xff]) reg name: uart_reg_block.rdata
	uart_stress_all_with_rand_reset	87146984643690873347436687145196985155621078111495151134289202303023282361222	170	UVM_ERROR @ 14786753329 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 14786753329 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_INFO @ 15220690829 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/947 UVM_ERROR @ 15288065829 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 12, clk_pulses: 0
	uart_stress_all	25696816540833247729003416296517551983897834715718138028033322781992538024919	85	UVM_ERROR @ 127005046363 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 127006319089 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 127006319089 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 127011591811 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0