Simulation Results: i2c

 
16/03/2026 16:04:31 DVSim: v1.15.0 sha: 2f20b6f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.07 %
  • code
  • 81.83 %
  • assert
  • 96.19 %
  • func
  • 83.19 %
  • line
  • 96.54 %
  • branch
  • 92.62 %
  • cond
  • 87.45 %
  • toggle
  • 89.66 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
85.71%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 19.270s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 6.960s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.670s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.650s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 1.810s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 0.960s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.120s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.650s 0.000us 1 1 100.00
i2c_csr_aliasing 0.960s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.790s 0.000us 0 1 0.00
host_stress_all 1 1 100.00
i2c_host_stress_all 641.490s 0.000us 1 1 100.00
host_maxperf 0 1 0.00
i2c_host_perf 1.250s 0.000us 0 1 0.00
host_override 1 1 100.00
i2c_host_override 0.710s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 167.970s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 115.370s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.900s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 12.440s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 2.720s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 101.340s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 25.410s 0.000us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.750s 0.000us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 2.090s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 193.500s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.290s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 10.130s 0.000us 1 1 100.00
i2c_target_intr_smoke 5.880s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.810s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 0.990s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 745.290s 0.000us 1 1 100.00
i2c_target_stress_rd 10.130s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 60.220s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.350s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 38.870s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 4.760s 0.000us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 5.270s 0.000us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.970s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.350s 0.000us 1 1 100.00
host_mode_config_perf 1 2 50.00
i2c_host_perf 1.250s 0.000us 0 1 0.00
i2c_host_perf_precise 5.140s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 25.410s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 3.440s 0.000us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 2.100s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.880s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.180s 0.000us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 3.180s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.500s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.600s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.640s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.160s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.160s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.670s 0.000us 1 1 100.00
i2c_csr_rw 0.650s 0.000us 1 1 100.00
i2c_csr_aliasing 0.960s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.760s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.670s 0.000us 1 1 100.00
i2c_csr_rw 0.650s 0.000us 1 1 100.00
i2c_csr_aliasing 0.960s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.760s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.510s 0.000us 1 1 100.00
i2c_sec_cm 0.990s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.510s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 16.610s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.850s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 12.310s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
i2c_host_perf 25869188557016377025753748215311706749541359451042368369790741771142804677302 82
UVM_ERROR @ 289092349 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 86436295296476380111013796349907843215357927350466873715168538980009495007424 86
UVM_ERROR @ 18283710 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 18283710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 50767730486296856036559669064680996788318688766991746028591357060331090037476 101
UVM_ERROR @ 1028997913 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 1028997913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_mode_toggle 94598646664077339314432285095216565981988472429395566854164110055036336816674 81
UVM_ERROR @ 14822222 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 14822222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 77516566140467847549317296009064127219647866276886161115674550955214595245459 84
UVM_ERROR @ 3876886888 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 3876886888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 6746177231275525042664937172578139367958319978279654313355747512281536772016 78
UVM_ERROR @ 79341018 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 157 [0x9d])
UVM_INFO @ 79341018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 71657162425604717917240340824765181724402761654906673997924816145735207467732 79
UVM_FATAL @ 10082204709 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10082204709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 75876006904824920803830056256520502516417258564882883860209589328675249282779 88
UVM_ERROR @ 498099183 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 498099183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 110768520796331250645425763986359137798449167472702044271845020452036554158320 78
UVM_ERROR @ 156144148 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 156144148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---